Optimum Load Impedance Research Articles

Multi-mode multi-band power amplifier module with high low-power efficiency**Project supported by the National Natural Science Foundation of China (No. 61201244).

Increasingly, mobile communications standards require high power efficiency and low currents in the low power mode. This paper proposes a fully-integrated multi-mode and multi-band power amplifier module (PAM) to meet these requirements. A dual-path PAM is designed for high-power mode (HPM), medium-power mode (MPM), and low-power mode (LPM) operations without any series switches for different mode selection. Good performance and significant current saving can be achieved by using an optimized load impedance design for each power mode. The PAM is tapeout with the InGaP/GaAs heterojunction bipolar transistor (HBT) process and the 0.18-μm complementary metal-oxide semiconductor (CMOS) process. The test results show that the PAM achieves a very low quiescent current of 3 mA in LPM. Meanwhile, across the 1.7–2.0 GHz frequency, the PAM performs well. In HPM, the output power is 28 dBm with at least 39.4% PAE and −40 dBc adjacent channel leakage ratio 1 (ACLR1). In MPM, the output power is 17 dBm, with at least 21.3% PAE and −43 dBc ACLR1. In LPM, the output power is 8 dBm, with at least 18.2% PAE and −40 dBc ACLR1.

An Output Matching Technique for a GaN Distributed Power Amplifier MMIC Using Tapered Drain Shunt Capacitors

This letter proposes an effective output matching technique using drain shunt capacitors with tapered capacitance values for a GaN distributed power amplifier MMIC to simultaneously obtain optimum load impedance for maximum output power of each transistor and phase velocity balance between input and output artificial transmission lines as well as length reduction of the transmission lines. To support its plausibility, a 2–6 GHz 10 W distributed power amplifier MMIC is designed and fabricated using a 0.25 $\mu$ m GaN HEMT process of WIN Semiconductors. Measurement of the S parameters and CW output power demonstrates successful operation of the proposed technique in the design frequency range.

An E-Band Power Amplifier With Broadband Parallel-Series Power Combiner in 40-nm CMOS

This paper describes a fully integrated E-band power amplifier (PA) in 40-nm CMOS. The design and layout of the unit PA stage is optimized to achieve high output power while maintaining high power gain. A broadband parallel-series power combiner is proposed to provide the PA stage optimum load impedance across the complete E-band. The complete PA achieves a measured saturated output power of 20.9 dBm with more than 15-GHz small-signal $-$ 3-dB bandwidth and 22% power-added efficiency (PAE) at 0.9-V supply. The in-band variation of $-$ 1-dB compressed power $(P_{1 {\rm {dB}}})$ is only $\pm$ 0.25 dB. This is the first reported silicon-based PA that covers both 71–76- and 81–86-GHz bands with uniform gain, output power, and PAE.

Real-time load impedance optimization for radar spectral mask compliance and power efficiency

This paper presents a fast optimization algorithm for power amplifiers in radar transmitters based upon a metric designed to assess spectral mask compliance. The search finds the load impedance maximizing the power-added efficiency (PAE) while providing compliance with the assigned spectral mask. Measurement results illustrate consistency in the chosen optimum values of efficiency, while spectral mask requirements are consistently met at the optimum load impedances chosen by the search. This algorithm will allow adaptive radar transmitter amplifiers to quickly adjust their load impedances to change frequency bands of operation, change spectral output properties based on nearby spectrum users, and meet dynamically varying spectral mask requirements.

A Maximum Efficiency Point Tracking System for Wireless Powering of Biomedical Implants

Inductive power transfer systems are widely used to supply the current generation of biomedical implants. However, the power transfer efficiency is highly dependent on both the mutual coupling of the coils and the load impedance of the implant side. To overcome the challenge of time-dependent coil orientation and load impedance changes due to different power consumption levels, a maximum efficiency point tracking (MEPT) system for inductive links is presented within this work. After characterizing the momentary mutual inductance of the transmission channel, the designed system calculates the optimum load impedance and performs a dynamic impedance matching by emulating this optimum load with an input voltage-controlled switching regulator. Therefore, the presented system is capable of extracting energy at the best case efficiency for a wide range of real loads. The implemented system features a small system size (14 x 14 mm2) and a low self-consumption of only 250 μW, while providing up to 100 mW to the load.

Doherty power amplifier with enhanced in‐band load modulation for 100 MHz LTE‐advanced application

ABSTRACTThis article presents a modified GaN Doherty power amplifier (PA) for 100 MHz long‐term evolution (LTE)‐advanced application at 2.5 GHz. To improve load modulation and consistency of the output power and efficiency in the operation bandwidth, a method was proposed by choosing optimal load impedances in Class C mode, properly increased gate bias voltage and optimized input matching network for the design of the peaking amplifier. When driven with 100 MHz LTE‐advanced signals, the designed PA achieves adjacent channel leakage ratio of −49 dBc after digital predistortion at 9 dB back‐off output power of about 40.5 dBm with efficiency of 42%. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:391–395, 2015

A Linearized 2–3.5 GHz Highly Efficient Harmonic-Tuned Power Amplifier Exploiting Stepped-Impedance Filtering Matching Network

This letter presents the analysis, implementation and experimental results of a broadband highly efficient power amplifier (PA) using harmonic-tuned method for long-term evolution (LTE)-advanced application. Load-pull simulation has been employed to obtain the optimal load impedances, especially the second harmonic impedances, for high efficiency and output power over wide bandwidth. A stepped-impedance low-pass matching network was then designed to achieve the desired impedance transformation. Experimental results show that the PA achieves 64%-76% efficiency and higher than 40 dBm output power over the frequency band from 2 to 3.5 GHz. When driven by a 100 MHz LTE-advanced signal at an average output power of 33.5 dBm, the average efficiency of 33.8%, 34.9%, and 37.8% was measured at 2.15, 2.55, and 3.45 GHz, respectively. The corresponding adjacent channel leakage ratio can be linearized to about -48 dBc by using digital pre-distortion technique.

Spherical Mode-Based Analysis of Wireless Power Transfer Between Two Antennas

A method is presented to analyze the maximum power transfer efficiency of a wireless power transfer system and its electromagnetic fields via spherical modes. The Z-parameter and Y-parameter for two coupled antennas are derived using the antenna scattering matrix and an addition theorem. In addition, formulas for calculating the maximum power transfer efficiency and optimum load impedance are presented. A formula is derived to calculate the electromagnetic field generated by a wireless power transfer system from the antenna scattering matrix.

Characterization of Class-F Power Amplifier With Wide Amplitude and Phase Bandwidth for Outphasing Architecture

A 2.14 GHz gallium nitride class-F power amplifier (PA) achieving both high efficiency and phase linearity over a wide frequency range is presented. The broadband PA is designed as one channel of outphasing architecture in cellular base-stations and analyzed in amplitude and phase domains. In amplitude domain, the PA exhibits measured maximum power added efficiency (PAE) of 80.1% with an output power of 40.7 dBm at 2 GHz. The PA achieves PAE higher than 55% over 500 MHz frequency range. The optimum second-harmonic load impedance enables the broadband operation. In phase domain, phase linearity of the PA is characterized by using phase modulation signals derived from single-carrier 10 MHz, two-carrier 40 MHz, and two-carrier 60 MHz long term evolution signals with 6.5 dB peak-to-average power ratio.

고조파 정합 기법을 이용한 고효율 GaN HEMT 전력 증폭기

본 논문에서는 고조파 정합 기법을 이용하여 고효율 GaN HEMT 전력 증폭기를 설계 및 제작하고, 그 특성을 측정하였다. 고효율 특성을 얻기 위해 고조파 로드풀 시뮬레이션을 활용하였다. 즉, 기본 주파수뿐만 아니라 2차, 3차 등의 고조파에서 최적의 부하 임피던스를 찾아내었다. 이러한 고조파 로드풀 시뮬레이션 결과를 바탕으로 출력 정합 회로를 설계하였다. 제작한 전력 증폭기는 중심 주파수 1.85 GHz에서 선형 전력 이득 20 dB 및 33.7 dBm의 <TEX>$P_{1dB}$</TEX>(1 dB gain compression point) 특성을 보였다. 그리고, 출력 전력 38.6 dBm에서 80.9 %의 최대 전력 부가 효율(Power Added Efficiency: PAE)을 나타냈으며, 이는 기존에 설계된 고효율 전력 증폭기와 비교했을 때 아주 우수한 효율 특성이다. 또한, W-CDMA 신호입력에 대한 측정 결과, 28.4 dBm의 평균 출력 전력에서 27.8 %의 PAE와 5 MHz offset 주파수에서 -38.8 dBc의 ACLR (Adjacent Channel Leakage Ratio)을 보였다. 그리고, 다항식 맞춤 방식의 디지털 전치 왜곡(Digital Predistortion: DPD) 선형화 알고리듬을 구현하여 제작된 전력 증폭기의 ACLR을 6.2 dB 정도 향상시킬 수 있었다. In this paper, we present the design, fabrication and measurement of high efficiency GaN HEMT power amplifier using harmonic matching technique. In order to achieve high efficiency, harmonic load-pull simulation is performed, that is, the optimum load impedances are determined at <TEX>$2^{nd}$</TEX> and <TEX>$3^{rd}$</TEX> harmonic frequencies as well as at the fundamental. Then, the output matching circuit is designed based on harmonic load-pull simulation. The measurement of the fabricated power amplifier shows the linear gain of 20 dB and <TEX>$P_{1dB}$</TEX>(1 dB gain compression point) of 33.7 dBm at 1.85 GHz. The maximum power added efficiency(PAE) of 80.9 % is achieved at the output power of 38.6 dBm, which belongs to best efficiency performance among the reported high efficiency power amplifiers. For W-CDMA input signal, the power amplifier shows a PAE of 27.8 % at the average output power of 28.4 dBm, where an ACLR (Adjacent Channel Leakage Ratio) is measured to be -38.8 dBc. Digital predistortion using polynomial fitting was implemented to linearize the power amplifiers, which allowed about 6.2 dB improvement of an ACLR performance.

A Wideband Power Amplifier in 45 nm CMOS SOI Technology for X Band Applications

A fully-integrated wideband power amplifier (PA) operating in 9-15 GHz range is implemented in a standard 45 nm CMOS SOI technology. The PA is designed with three dynamically-biased stacked Cascode cells (6 stacked transistors) to overcome the low breakdown voltages of nanoscale CMOS transistors. The stacked Cascode cells ensure stable operation and facilitate high gain, and high optimum load impedance, leading to high output power, high efficiency and good linearity characteristics over the entire bandwidth. The unbalanced amplitude and phase of drain-source voltage signals caused by internodal parasitic capacitance are equalized by adjusting the sizing of transistors. With a supply voltage of 4.8 V at 12 GHz, the measured saturated output power and linear power are 22.5 dBm and 19.2 dBm, respectively, while the peak power-added efficiency (PAE) is 19.2%. At a reduced power supply of 3.6 V, the PA achieves peak PAE of 25.7% where the drain efficiency reaches 40.7%. Including its pads, the PA occupies a compact chip area of 0.22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Rapid Wireless Capacitor Charging Using a Multi-Tapped Inductively-Coupled Secondary Coil

This paper presents an inductive coupling system designed to wirelessly charge ultra-capacitors used as energy storage elements. Although ultra-capacitors offer the native ability to rapidly charge, it is shown that standard inductive coupling circuits only deliver maximal power for a specific load impedance which depends on coil geometries and separation distances. Since a charging ultra-capacitor can be modeled as an increasing instantaneous impedance, maximum power is thus delivered to the ultra-capacitor at only a single point in the charging interval, resulting in a longer than optimal charging time. Analysis of inductive coupling theory reveals that the optimal load impedance can be modified by adjusting the secondary coil inductance and resonant tuning capacitance. A three-tap secondary coil is proposed to dynamically modify the optimal load impedance throughout the capacitor charging interval. Measurement results show that the proposed architecture can expand its operational range by up to 2.5 × and charge a 2.5 F ultra-capacitor to 5 V upwards of 3.7 × faster than a conventional architecture.

A 16.9 dBm InP DHBT W-band power amplifier with more than 20 dB gain

A two-stage MMIC power amplifier has been realized by use of a 1-μm InP double heterojunction bipolar transistor (DHBT). The cascode structure, low-loss matching networks, and low-parasite cell units enhance the power gain. The optimum load impedance is determined from load-pull simulation. A coplanar waveguide transmission line is adopted for its ease of fabrication. The chip size is 1.5 × 1.7 mm2 with the emitter area of 16 × 1 μm × 15 μm in the output stage. Measurements show that small signal gain is more than 20 dB over 75.5–84.5 GHz and the saturated power is 16.9 dBm @ 79 GHz with gain of 15.2 dB. The high power gain makes it very suitable for medium power amplification.

Integrated Design of a Class-J Power Amplifier

This paper discusses the design of a monolithic microwave integrated circuit (MMIC) class-J GaN power amplifier (PA). Theoretical derivations of optimum load impedances, output power, and efficiency are presented to demonstrate their dependence on the quality factor of the integrated inductor used in the output matching network. A group of design curves are obtained to select the optimum transistor size and impedance according to the required output power and efficiency for a given inductor loss. An analytical-based design methodology using the design curves is proposed. To verify the accuracy of this analytical design approach, an integrated 0.5-W 15-V monolithic microwave integrated circuit PA is fabricated in 0.8-μm GaN technology. The PA exhibits greater than 50% drain efficiency over 825 MHz, from 2.25 to 3.075 GHz.

Coupling study of a novel thermocompressor driven pulse tube refrigerator

The impedance match is important for the efficiency and available acoustic power of thermocompressor (TCP). The filling pressure, hot end temperature, reservoir volume and opening of orifice were changed to test the optimum load impedance for the maximum acoustic power by RC (Resistor and Capacitor) load method. To make use of the acoustic power efficiently, a pulse tube refrigerator (PTR) was designed based on this impedance to match the TCP and relative coupling experiments were conducted for the first time. The refrigerating performance of PTR was observed and the lowest no-load temperature of 70.4 K was obtained at its optimum working frequency 5.6 Hz. Also, the performance characteristics and total impedances of three different PTRs were compared to verify the rationality of the impedance matching method in this paper. The calculation results agree well with the substantial experiments and further optimization methods were also proposed.

Addition of a series spring to a lumped element model of a novel thermoacoustic refrigerator

A lumped element model is introduced for an “in-line” traveling-wave thermoacoustic refrigerator, based on a recent patent by Backhaus and Keolian [US Pat. No. 7,908,856 (22 Mar 2011)]. This model couples three electro-mechanical motors to the acoustical domain using a flexure sealed piston. Results of this lumped-element model were found to be in good agreement with a DELTAEC model. Since large displacements result in flexure fatigue, the addition of a series spring between the motor and piston was evaluated to reduce flexure seal displacement while matching the optimum load impedance. The assignment of the correct dynamic mass of the series spring when both the motor and flexure ends of the spring are moving has not been addressed previously in the literature. To determine the two effective masses required at each end of the spring, the spring is discretized into a large number of elements and is converted into a simplified circuit model to assign values to lumped-element components. These values depend upon an initial knowledge of both end velocity magnitudes and phases. This enables an iterative solution for the effective spring masses since velocities need to be known for effective masses to be determined and vice versa. [Work supported by the Applied Research Laboratory and the U.S. Department of Energy.]

Harmonic-Tuned High Efficiency RF Oscillator Using GaN HEMTs

A harmonic-tuned high efficiency oscillator is designed using gallium nitride (GaN) high electron mobility transistors (HEMTs). The harmonic load-pull simulation is performed to find the voltage and current waveforms and to locate the optimum load impedance for high efficiency operation of the transistor. Then, the feedback network for the oscillation is synthesized based on the load-pull data. The series resonant circuit is employed in the feedback network to provide open circuit to the load network at harmonic frequencies. Therefore, the load network can be designed separately from the feedback network to present the optimum harmonic load impedances. In this way, the transistor in the oscillator can achieve the optimum voltage and current waveforms determined by the harmonic load-pull simulation. The fabricated GaN oscillator using the proposed design approach shows the maximum efficiency of 80.2% and output power of 35.1 dBm at 2.42 GHz under drain bias voltage of 22 V.

밀리미터파 대역 제2고조파 고효율 생성을 위한 부하 임피던스의 최적화 방법

The objective of this paper is to present a quantitative analysis leading to the assessment of optimum terminating impedances in the design of active frequency multipliers. A brief analysis of the basic principal of the GaAs FET frequency multiplier is presented. The analysis is outlined in bias optimization and drive power determination. Utilizing the equivalent circuit model of GaAs FET, we have simulated the optimized load impedance for the maximum output of the active frequency multipliers. The C-class and reverse C-class frequency doublers have been fabricated and the load impedances have been measured. The experimental results are in good agreement with the estimated results in the simulation with the accuracy of 90%.

Measurement-based methodology to design harmonic-loaded oscillators using real-time active load pull

This study presents a measurement-based methodology to efficiently design a harmonic-loaded oscillator at a targeted frequency using the novel multi-harmonic real-time active load-pull (RT-ALP) technique. Owing to the speed of the RT-ALP technique the design procedure is quasi-interactive. Simulations were first used to design a stable negative resistance around 2.5 GHz using series feedback with a variable tapped capacitor to tune the negative resistance in the desired frequency band. The device lines were then measured for characterising the negative-resistance device versus input power at 2.5 GHz. Using RT-ALP the optimal second- and third-harmonic load impedances that provide the maximum output power were then determined. Two different load circuits were then designed and implemented to approach the optimal multi-harmonic load impedances and realise a stand-alone oscillator. In accordance with the Kurokawa theory, a reasonable agreement is obtained in terms of output power and frequency of oscillation between the stand-alone oscillator built and the multi-harmonic load-pull measurements demonstrating the viability of the proposed method. To our knowledge, this is the first fabricated oscillator designed with experimental active load-pull to consider third-harmonic tuning.

A CMOS Broadband Power Amplifier With a Transformer-Based High-Order Output Matching Network

A transformer-based high-order output matching network is proposed for broadband power amplifier design, which provides optimum load impedance for maximum output power within a wide operating frequency range. A design methodology to convert a canonical bandpass network to the proposed matching configuration is also presented in detail. As a design example, a push-pull deep class-AB PA is implemented with a third-order output network in a standard 90 nm CMOS process. The leakage inductances of the on-chip 2:1 transformer are absorbed into the output matching to realize the third-order network with only two inductor footprints for area conservation. The amplifier achieves a 3 dB bandwidth from 5.2 to 13 GHz with 25.2 dBm peak and 21.6% peak PAE. The EVM for QPSK and 16-QAM signals both with 5 Msample/s are below 3.6% and 5.9% at the output 1 dB compression point. This verifies the PA's capability of amplifying a narrowband modulated signal whose center-tone can be programmed across a large frequency range. The measured BER for transmitting a truly broadband PRBS signal up to 7.5 Gb/s is less than 10 , demonstrating the PA's support for an instantaneous wide operation bandwidth.