Optical Receiver Front-end Research Articles

A 10-Gb/s low-power inverter-based optical receiver front-end in 0.13-[formula omitted] CMOS process

In the design of CMOS optical receivers, it is challenging to compromise the bandwidth, noise, and gain of the transimpedance amplifier (TIA). The inverter-based cascaded structure is often used in TIA designs. However, the traditional 3-stage TIA needs bandwidth expansion techniques to get good performance. In the designed front-end, we propose a 5-stage cascaded TIA that achieves performance improvement without using bandwidth expansion technique. Besides, the stability of the main amplifier (MA) is improved by adopting a feed-forward compensation technique. Designed in a 0.13-μm CMOS process, the proposed front-end exhibits a bandwidth of 8.9 GHz, a transimpedance gain of 123.5 dB Ω and an average input-referred noise of 12.2 pA/Hz. The whole circuit consumed 19.1 mW from mixed input of 1 V and 1.5 V supply voltages.

Design framework for inverter cascode transimpedance amplifier using Gm/ID based PSO applying design equations

This paper presents a framework for the design of the inverter cascode (InvCas) transimpedance (TIA) for the optical receiver's front-end. The framework combines the particle swarm optimization (PSO) evolutionary algorithm with the gm/ID methodology to calculate the required circuit parameters needed to obtain the target specifications entered by the designer. The framework relies on the derived circuit equations to define the design space and evaluate the performance using the parameters calculated by the gm/ID and PSO. This technique speeds up the design process by avoiding the need for Spice simulation to assess the fitness of each particle during the optimization process. The proposed framework is implemented in a Matlab program utilizing the framework that takes target specifications as an input and provides the design parameters of the particle with the best circuit performance satisfying these specifications as an output. The framework is tested using the 130 nm CMOS technology to produce three different designs each targeting a different bandwidth and gain for different optical communications data rates while optimizing the power and noise performance of each design. All the evaluated designs achieved the required specifications and show superior performance compared with TIA state-of-the-art.

A 61.2-dBΩ, 100 Gb/s Ultra-Low Noise Graphene TIA over D-Band Performance for 5G Optical Front-End Receiver

This work reports in first time a 100-Gb/s, ultra-low noise, variable gain multi-stagger tuned transimpedance amplifier (VGMST-TIA) over the D-band performance. The whole work is binding into two phases. The first phase involves the modeling and characterization of graphene field-effect transistor (GFET) with an optimized transition frequency of operation. While in the second phase, a TIA design employs a T-shaped symmetrical L-R network at the input, which mitigates the effect of photo diode capacitance and achieves a D-band of operation. The proposed work uses a VGMST to establish TIA, which realizes optimum noise performance. The high gain 3-stage VGMST-TIA effectively minimizes the white noise and illustrates a sharp out-of-band roll-off to achieve considerable noise reduction at high frequencies. The active feedback mechanism controls the transimpedance gain by tuning the control voltage which results better group delay. Besides, an L-C circuit is employed at the output to enhance bandwidth. The full TIA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using 0.065-μm process. The TIA achieves a flat transimpedance gain of 61.2 dBΩ with ± 9 ps group delay variation over the entire bandwidth. The proposed TIA measured an impedance bandwidth of 0.2 THz with ultra-low input-referred noise current density of 2.03 pA/√Hz. The TIA supports a 100-Gb/s data transmission due to large bandwidth; therefore, a bit-error-rate (BER) less than 10−12 is achieved. The chip occupies an area of 0.92 * 1.34 mm2 while consuming power of 21 mW under supply of 1.8 V.

Noise Analysis and Design Considerations for Equalizer-Based Optical Receivers

Optical receiver front ends that are intentionally designed to have a bandwidth low enough that significant inter-symbol interference (ISI) is introduced are becoming commonplace. Although the resultant ISI must be removed using an equalizer, the lower bandwidth allows for higher gain in the front-end’s first stage, lower input-referred noise, and fewer gain stages. With fewer main-amplifier stages, power dissipation is reduced. The noise analysis of these front ends presents several challenges. This paper derives integrated input-referred noise for inverter-based shunt-feedback transimpedance amplifiers from first principles and highlights the importance of correctly estimating the gain and noise bandwidth of the receiver. The notion of the effective gain of the receiver is introduced, which is lower than the midband gain typically used in noise calculations. The analysis of the inverter-based TIA is used to discuss the important design tradeoffs depending on the type of equalizer used. Integrated input-referred noise is derived and compared for front ends using decision-feedback equalizers (DFEs), continuous-time linear equalizers, and feed-forward equalizers. The simulation results show that a DFE-based receiver achieves the lowest input-referred noise.

An Inverter-Based, CMOS, Low-Power Optical Receiver Front-End

ABSTRACTIn this paper, a low-power optical receiver front-end which consists of a transimpedance amplifier (TIA) and three stages of limiting amplifier (LA) for 2.5 Gb/s applications is proposed in 0.18 µm CMOS technology. The proposed TIA benefits from a modified inverter structure, in which the input resistance is properly reduced due to the use of diode-connected transistors in comparison with conventional inverter circuit. Also, an active inductor is used in parallel with a diode-connected transistor at the output node, which provides a low output resistance, while it resonates with the load capacitance to extend the −3 dB frequency bandwidth. Moreover, three stages of LAs are used to obtain extra gain, in which each LA cell uses active inductor load. However, HSPICE simulations for the proposed TIA circuit show a 42.24 dBΩ transimpedance gain, 1.96 GHz frequency bandwidth, 11.7 pA/√Hz input referred noise, and only 972 µW of power consumption at 1.5 V supply. Also, simulation results for the whole receiver system show a 75.6 dB gain, 1.7 GHz frequency bandwidth, and 6.54 mW of power consumption at 1.5 V supply. Finally, simulation results indicate that the proposed receiver system has good performances to be used as a low-power optical receiver front-end.

Integrated RF Passive Low-Pass Filters in Silicon Photonics

The integration of passive radio frequency (RF) components, such as resistors, capacitors, and inductors, requires a relatively large area on complementary metal—oxide—semiconductor chips, which is not cost-effective in developing optical receiver front-ends. This could be addressed by implementing passive RF components on silicon photonics chips. In this letter, we present an on-chip passive RF low-pass filter coupled to an integrated photodetector. This letter demonstrates that passive RF analog processing can be implemented in a commercial silicon photonics platform. The performance of the implemented RC filters is reported at frequencies up to 15 GHz.

DEVELOPMENT OF OPTICAL WIRELESS RECEIVER AMPLIFIER USING HYBRID ENHANCEMENT

In the new communication era, signal will be transmit to the receiver via wireless. However, the signal might be loss during the transmission. Therefore, the signal received at the receiver is totally not originally from the transmitter. In some cases the signal must be amplified. This project will focuses on the concept of wireless optical in receiver communication system. The objectives of this project is to design a receiver amplifier using hybrid bandwidth enhancement in the approximately of Giga hertz range. The receiver amplifier is designed using Micro-Cap. The configuration of this design receiver is by using combination of bootstrapping and cascade technique. Bootstrapping technique offers the reduction on the photo detector capacitances which is the main limiting factor for the bandwidth of optical wireless front-end receiver. While, the cascade technique is used to arrange the electrical components such as transistor. Using the designed receiver Bootstrap Amplifier with Double Peaking Coil has been designed and fabricated. The cut-off frequency for this circuit is 400MHz.

A CMOS Low-Power Optical Front-End for 5 Gbps Applications

ABSTRACTIn this paper, a new low-power optical receiver front-end is proposed in 90 nm CMOS technology for 5 Gb/s AApplications. However, to improve the gain-bandwidth trade-off, the proposed Trans-Impedance Amplifier (TIA) uses an active modified inverter-based topology followed by a common-source amplifier, which uses active inductive peaking technique to enhance the frequency bandwidth in an increased gain level for a reasonable power consumption value. The proposed TIA is analyzed and simulated in HSPICE using 90 nm CMOS technology parameters. Simulation results show a 53.5dBΩ trans-impedance gain, 3.5 GHz frequency bandwidth, 16.8pA/√Hz input referred noise, and 1.28 mW of power consumption at 1V supply voltage. The Optical receiver is completed using three stages of differential limiting amplifiers (LAs), which provide 27 dB voltage gain while consume 3.1 mW of power. Finally, the whole optical receiver front-end consumes only 5.6 mW of power at 1 V supply and amplifies the input signal by 80 dB, while providing 3.7 GHz of frequency bandwidth. Finally, the simulation results indicate that the proposed optical receiver is a proper candidate to be used in a low-power 5 Gbps optical communication system.

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm2, is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10−12at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.

A 30–75 <inline-formula> <tex-math notation="LaTeX">$\text{dB}\Omega$</tex-math> </inline-formula> 2.5 GHz 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu\text{m}$</tex-math> </inline-formula> CMOS Receiver Front-End With Large Input Capacitance Tolerance for Short-Range Optical Communication

This paper describes the design and implementation of a linear optical receiver front-end for short range optical communication applications in 0.13-μm CMOS technology. While conventional optical receivers are typically implemented using limiting amplifiers (LA), emerging optical systems are expected to employ advanced modulation schemes, which require preserving the signal envelope. The proposed linear optical receiver architecture utilizes super-Gm transimpedance amplification with common-mode restoration and constant settling time automatic gain control (AGC) with background illumination cancellation to preserve the signal linearity while tolerating capacitance up to 15 pF for large area photo-detectors. Linearity aware design of transimpedance amplifiers (TIA), variable gain control (VGA), and post amplifiers (PA) are discussed before introducing an exponential generator based on the parasitic BJTs available in the used technology. Consuming 40 mW from a 1.2 V supply in the presence of ~15 pF input capacitance, the circuit achieves a binary modulation data rate of 5 Gbps with an input sensitivity of ~ 65 μA maintaining a bit-error rate (BER) <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . S-parameter measurements show a constant -3 dB bandwidth of 2.5 GHz for a wide dynamic range of ~45 dB (30-75 dBΩ) with dB-linearity error better than ±1 dB. To demonstrate the optical functionality of the architecture, an external photodiode (PDCS70T-GS) is directly wirebonded to the chip. Optical measurements confirm a sensitivity of -9.5 dBm (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) at a highest data rate of 5 Gb/s (λ = 680 nm). The noise and linearity performance of the receiver is verified using input referred integrated noise and 1 dB-compression point measurements for different gain settings.

Design of a high gain and power efficient optical receiver front-end in 0.13 μM RF CMOS technology for 10 Gbps applications

In this paper, two versions of a complete RF front-end for a 10 Gbps optical receiver are presented. The RF front-end consists of a transimpedance amplifier and a limiter amplifier. Two versions of the TIA amplifiers are proposed. The first topology has 54 dB transimpedance gain, 11.5 GHz bandwidth and has a input current noise density of only 6.8pA/Hz. The second topology is composed by a cascade os two inverters. This topology has 48 dB transimpedance gain, 11.2 GHz bandwidth, a input current noise density of 8.9pA/Hz and occupies an area of only 0.048 mm2. The limiter amplifier for both optical receivers is a five stage cherry-hooper amplifier with active inductors optimized for low power. The main amplifier has 38 dB gain, 9.8 GHz Bandwidth, 69 mW of power consumption and only 0.171 mm2 of die area. The complete RF front-end is fully integrated and has 10 GHz bandwidth. The circuits were designed in 0.13 μm RF CMOS technology. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1499–1504, 2016

Symmetric signal and local oscillator polarization diverse coherent optical receiver.

An improved coherent optical receiver architecture that compensates for a random drift in the state of polarization (SOP) of both the signal and the local oscillator (LO) is presented for the first time. The proposed architecture comprises two conventional coherent optical receiver front-ends in tandem, where the SOP of the LO is first divided into its two orthogonal components and then distributed to each coherent optical receiver front-end module. Two distinct methods of polarization diversity recovery of the modulation based on the MRC technique and an eigenvalue-eigenvector decomposition of the covariance matrix have been used to effectively recover the transmitted signal. The concept is validated by numerical simulations, where a differential quadrature phase-shift keyed (DQPSK) modulated signal with a random time-varying SOP is first generated. After its mixing with a LO also possessing a random time-varying SOP, the algorithms that have been developed are provided with eight input variables to be digitally processed. The constellation diagrams corresponding to the recovered DQPSK modulation obtained using the two polarization diversity methods are presented.

Optical Coherent Receiver Front End for Inter-Satellite Laser Communication Link

This paper presents the new concept of optical coherent receiver front end which can obtain optical phase error signals in PSK (Phase Shift Keying) communication data as well as spatial tracking error without any extra tracking sensor, leading to downsizing of inter-satellite laser communication terminals. This new receiver front end consists an optical 90 deg hybrid mixer with free space optical components, segmental photo detectors and RF electronics, to realize not only balanced detection of both in-phase and quadrature components but also heterodyning detection of tip/ tilt error signals.

A CMOS lock-in amplifier for low-power biomedical applications

An analogue Lock-In Amplifier (LIA) is employed in an optical receiver front end to retrieve signals from an extremely noisy environment. The conventional LIA consists of a current source, Transimpedance Amplifier (TIA), set of active Gm-C filter and Phase Locked Loop (PLL). In this work, a high gain low power TIA making use of Operational Transconductance Amplifier (OTA) is proposed. This structure has a 54% improvement in gain and consumes 8% lesser power compared to replica biasing TIA. The gain boosting circuit in the NMOS current steering charge pump reduces the power consumption by 38% compared to conventional structure. In the modified Phase Frequency Detector (PFD), True Single Phase Clock (TSPC) logic is utilised which consumes 50% lesser power compared to conventional design. So, the low power LIA designed with proposed structures can be used for low power biomedical applications. Simulations are done using Cadence Spectre, GPDK 180 nm technology.

CMOS Transimpedance Amplifier for Visible Light Communications

Transimpedance amplifiers (TIAs) play a pivotal role in the optical wireless receiver front end. To exploit its distinctive open-loop characteristics, a feedback transimpedance amplifier comprising a feedforward current amplifier (CA-TIA) is investigated. Attributing to the small input impedance with a high-pass response of its feedforward gain element, the bandwidth of the CA-TIA is less sensitive to the TIA gain. The analysis and implementation of the CA-TIA are experimentally validated.

Sensitivity modeling of binary optical receivers.

The sensitivity characteristics of optical receiver frontends for high-speed data communications depend on modulation format, detector type, and specific operational constraints. A general mathematical model of the receiver sensitivity that fits to analytical as well as measured data is required to compare different receiver implementations and assess the reliability of data links under varying received power as common in free-space optical communication links. In this paper, a new approach based on Q-factor modeling is presented, compared with analytical receiver models, and applied to a multitude of exemplary receiver implementations. A methodology is introduced to generally apply the model to ideal or practical binary optical receiver frontends.

A 5-Gb/s Noise Optimized Receiver Using a Switched TIA for Wireless Optical Communications

This paper reports a systematic approach for designing a low noise and low power optical receiver targeting high sensitivity imaging architectures for optical wireless communications. For line of sight tracking in optical wireless communications, a switching matrix is employed between the pixel/photodetector array and the transimpedance (TIA) amplifier. An optimization procedure is introduced to balance various performance parameters in the optical receiver front end when including the effect of the switch. The presented optical receiver consists of a low noise, wideband TIA, where noise and stability are optimized using a series inductor at the input. The TIA is followed by a limiter with offset cancellation and 50 Ω output buffer capable of 900 mV p-p differential output swing, over the 50 Ω resistance of the BERTScope. The receiver implemented in the IBM 130 nm CMOS technology, achieves a bit error rate of 10-12 at 5-Gb/s corresponding to 2.8 μA current at the input and at 4-Gb/s corresponding to 2.1 μA input current, in presence of 1 pF input capacitance representing the photodiode. The total power consumption including the on chip 50 Ω differential output buffer is 68 mW from 1.5 V DC supply. The die area including bonding pads and output buffer is 1106 μm × 895 μm.

Optical receiver front end for optically powered smart dust

SummaryThe ability to create and direct beams of light means that optical communications potentially offer a large power advantage over RF communications for sensor networks. This paper presents an optically powered receiver front end for wireless optical communications. A complete optical receiver front end including a photodetector, clock and Manchester data recovery circuits has been fabricated using the UMC 180 nm CMOS process. A novel modulation scheme is described that has been devised so that this front end can recover the clock and Manchester data from an optical beam. Experimental results show that the total current consumption of the optical receiver front end is as low as 18.8 nA for a 0.5 V supply when a 1 kbps Manchester data and 8 kHz clock signal are successfully recovered. This means that photodiodes on the same substrate as the front end circuits extract enough power from the communications beam to allow the front end to work at distances of up to 10 m from the transmitter. Copyright © 2013 John Wiley &amp; Sons, Ltd.

Design of a CMOS Optical Receiver Front-End Using 0.18 μm Technology

This paper reports design of a CMOS optical receiver front-end using 0.18 μm technology. Design process is current associated with photodiode using trans-impedance amplifier (TIA) for wide bandwidth, high gain, low input referred noise and wide dynamic range. The Automated Gain Control (AGC) voltage is used to provide variable gain for multilevel signals. This design is simulated in 0.18 μm UMC technology for the performance analysis. The best simulation results are reported the maximum TIA gain of 67.26 dB? at 0 V AGC followed by a post amplifier gain of 86.70 dB?. The bandwidth range is 7.03 GHz to 11.5 GHz corresponding to 0 - 3 V AGC respectively. The input referred noise level value is 43.86 pA/√Hz up to 10 GHz frequency. In addition authors have obtained the common mode rejection ratio (CMRR) is 72.42 dB and rectified group delay is 144.48 ps. Verification of the design, reported results are compared with earlier published work and improvements obtained in the present results.

Optical Front-End Receiver Design for Optical Wireless Communication System

This paper presents a bootstrapping technique that is applicable for various large window photodetectors by introducing a variable feedback capacitor to the front-end system. Two types of optical front-end receivers; Transimpedance amplifier (TIA) and Bootstrap transimpedance amplifier (BTA) were simulated and the performances of both architectures were compared. With the photodiode input capacitance compensation, the BTA improves the systems performance in which up to 670% increase was exhibited in the systems bandwidth. On the other hand, using the variable feedback capacitor in the circuit design, the fidelity of the system response was improved. This article also refers some recent patent on optical wireless receiver designs.