Optical Receiver Analog Front-end Research Articles

A 25 Gbps inductorless optical receiver analog front-end based the modified Cherry-Hooper amplifier for optical interconnect

In this paper, a 25 Gbps inductorless optical receiver analog front-end is presented. The inverter-based modified Cherry-Hooper amplifier is proposed and adopted as main stage of the optical receiver to extend the bandwidth by alleviating Miller capacitance. The optimization of shunt-feedback transimpedance amplifier is implemented by improving the gain bandwidth product of main amplifier. In multi-stage limiting amplifier, the staggered active feedback technique is used to boost the deteriorated bandwidth. Fabricated in a 55 nm CMOS technology, the whole chip occupies an area of 770 μm × 800 μm, and core area is only 100 μm × 400 μm. The measured 3-dB bandwidth reaches 21.7 GHz, sufficient for 25-Gbps operation. For an input voltage of 3 mVp-p, the chip achieves a BER = 10−12 at 25-Gbps PRBS7, and 320 mV differential output voltage is delivered. From the supply voltage of 1.2 V, the test chip consumes the power of 56 mW and exhibits the power efficiency of 2.3 pJ/s.

4-Channel, 100 Gbps Inductorless Optical Receiver Analog Front-End in CMOS for Optical Interconnect

In this paper, a 4-channel, 100 Gbps inductorless optical receiver analog front-end fabricated in a 55 nm bulk-CMOS technology is presented. Active feedback technique is widely adopted to improve the performance of the optical receiver without the area-occupied inductors. To alleviate the voltage headroom stress of the local feedback loop in traditional regulated cascode transimpedance amplifier, the common gate amplifier is inserted before the traditional common source feedback stage. And the cross-couple active feedback stage provides a negative signal path to extend the bandwidth of the local feedback loop. Multi-stage limiting amplifier with active negative and positive feedback stages are employed to extend bandwidth and acquire high gain simultaneously. The optical receiver was realized as 4-element arrays occupying the area of $800\,\,\mu \text{m}\,\,\times 1800\,\,\mu \text{m}$ , whereas the core area of each channel is just $275\,\,\mu \text{m}\,\,\times 650\,\,\mu \text{m}$ . The measured 3-dB bandwidth reaches 22.8 GHz, sufficient for 25-Gbps operation. For an input voltage of 2.5 mV $_{\text {p-p}}$ , the optical receiver achieves a BER $= 10^{-12}$ at 25-Gbps PRBS7, and 310 mV differential output voltage is delivered. From the supply voltage of 1.2 V, the test chip consumes the power of 226 mW and exhibits the power efficiency of 2.3 mW/Gb/s, when 25-Gbps PRBS31 is supplied.

A 10-Gb/s 0.18-μm CMOS Optical Receiver Front-End Amplifier

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is stimulation using a 0.18μm CMOS process. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The tiny photo current received by the receiver AFE is amplified to voltage swing of 400. The results indicate that, with a photodiode parasitic capacitance of 500fF and the bonding pad parasitic capacitance of 200fF between which a 2-mm bond wire is inserted at the input node, the AFE provides a conversion gain of up to 89.21 dB and 3 dB bandwidth of 9.78 GHz. Operating under a 1.8V supply, circuit power dissipation is 95 mW and its sensitivity is 18.5μA for BER of 10-12

A 40 Gbit/s fully integrated optical receiver analog front-end in 90 nm CMOS

A fully integrated 40 Gbit/s optical receiver analog front-end (AFE) including a transimpedance amplifier (TIA) and a limiting amplifier (LA) for short distance communication is described in this paper. The proposed TIA employs a modified regulated cascode (RGC) configuration as input stage, and adopts a third order interleaving active feedback gain stage. The LA utilizes nested active feedback, negative capacitance, and inductor peaking technology to achieve high voltage gain and wide bandwidth. The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV(p-p). Simulation results show that the receiver AFE provides conversion gain of up to 83 dBΩ and bandwidth of 34.7 GHz, and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA(rms).

Design and Implementation of 10-Gb/s Optical Receiver Analog Front-End in 0.13-.MU.m CMOS Technology

In this paper, a 10-Gb/s CMOS optical receiver analog front-end is designed and implemented in 0.13-μm CMOS technology. An optical receiver analog front-end includes a pre-amplifier and a post amplifier. To ensure 10-Gb/s operation, the effect of inherent photodiode parasitic capacitance should be suppressed. Thus, an advanced common-gate stage is exploited as the input stage of pre amplifier. To enhance the bandwidth without a passive inductor, a new post amplifier with active feedback and negative capacitance compensation techniques is proposed. A prototype chip has 98-dBΩ of trans-impedance gain (Z T ), corresponding 40-dB input dynamic range (5-μA to 500-μA) and minimum allowable input current (5-μA). Also, the receiver achieves the bandwidth of 7.5-GHz for 0.25-pF photodiode parasitic capacitance, and the measured optical sensitivity equals -18-dBm for 10 -12 bit error rate (BER).

A 10 Gbit/s Optical Receiver Analog Front-End with Input Parasitic Capacitance Immunization Technique

This paper presents a 10 Gbit/s SiGe optical receiver analog front-end (AFE) using input parasitic capacitance immunization technique to enhance bandwidth performance. The broadband technique can strongly reduce the total input capacitance of the optical receiver AFE. The 10 Gbit/s optical receiver AFE was realized in a standard 0.35 µm SiGe bipolar junction transistor complementary metal oxide semiconductor (BiCMOS) process. The measured performance results of the receiver AFE demonstrate a differential output swing of 600 mV under 50 Ω instrument loads, a peak-to-peak jitter (jitterp–p) of 28.28 ps, a root-mean-square jitter (jitterrms) of 4.47 ps, and an input sensitivity of -12.1 dBm, respectively, at a bit error ratio (BER) of 10-12 under a 10 Gbit/s 231-1 pseudo random binary sequences (PRBS) test pattern. The total circuit dissipates 180 mW under a 3 V supply, and the chip size is 700 ×760 µm2.

A 90-${\hbox {dB}}\Omega$ 10-Gb/s Optical Receiver Analog Front-End in a 0.18-$\mu{\hbox {m}}$ CMOS Technology

A 10-Gb/s 90-dBOmega optical receiver analog front-end (AFE), including a transimpedance amplifier (TIA), an automatic gain control circuit, and a postamplifier (PA), is fabricated using a 0.18-mum CMOS technology. In contrast with a conventional limiting amplifier architecture, the PA is consisted of a voltage amplifier followed by a slicer. By means of the TIA and the PA codesign, the receiver front-end provides a -3-dB bandwidth of 7.86 GHz and a gain bandwidth product (GBW) of 248.5 THz-Omega. The tiny photocurrent received by the AFE is amplified to a differential voltage swing of 900 mVpp when driving 50-Omega output loads. The measured input sensitivity of the optical receiver is -13 dBm at a bit-error rate of 10-12 with a 231-1 pseudorandom test pattern. The optical receiver AFE dissipates a total power of 199 mW from a 1.8-V supply, among which 35 mW is consumed by the output buffer. The chip size is 1300 mumtimes1796 mum

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.