Optical Proximity Effect Research Articles

Robust and efficient inverse mask synthesis with basis function representation.

Mask optimization is essential in the resolution scaling of optical lithography due to its strong ability to overcome the optical proximity effect. However, it often demands extensive computation in solving the nonlinear optimization problem with a large number of variables. In this paper, we use a set of basis functions to represent the mask patterns, and incorporate this representation into the mask optimization at both the nominal plane and various defocus conditions. The representation coefficients are updated according to the gradient to the coefficients, which can be easily obtained from the gradient to the pixel variables. To ease the computation of the gradient, we use an adaptive method that divides the optimization into two steps, in which a small number of kernels is used as the first step, and more kernels are used for fine optimization. Simulations performed on two test patterns demonstrate that this method can improve the optimization efficiency by several times, and the optimized patterns have better manufacturability compared with regular pixel-based representation.

Pupilgram control for optical proximity effect matching

Pupilgram control for optical proximity effect matching

Design intent application to tolerance-based manufacturing system

Continuous shrinkage of the design rule in large-scale integrated circuit devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension tolerance for each object, considering design intent in terms of electrical behavior, and assigning the tolerance for each process step. However, once the design data are converted to layout data and signed off, most of the design intent is abandoned and unrecognized in the process phase. Thus, uniform and redundant tolerance is used, and therefore, excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intent has been discussed. Using a 40-nm node test chip, electrically critical spots, such as timing, cross-talk noise, electromigration, with small margins are extracted, assigned to the physical layout, and utilized in the manufacturing process. The flow is applicable for optical proximity effect correction (OPC) turnaround time reduction, optimization of OPC/lithography compliance check (LCC) specification, and failure-analysis acceleration. Consequently, a design-intent-aware manufacturing system is promising for realizing proper process specifications and computational cost reduction, in addition to yield enhancement.

Intentional Distortion of Transistor Shape to Improve Circuit Performance

A mixed-mode 3-D simulation study has been performed for ring oscillators made of 30-nm planar CMOS transistors with nonrectangular channel shapes. Nonrectangular shapes happen unintentionally due to optical proximity effects and can also be introduced intentionally. Transistors with large drains are shown to degrade ring-oscillator performance, whereas transistors with large sources are shown to simultaneously increase the ring-oscillator frequency by 25% and reduce the leakage current by a factor of three.

High Yield Patterning with Simplified DFM Rules in Sub-100nm Process Technologies

Traditional DFM methods of sub-100nm technologies have emphasized on the offering of optical proximity effect driven DFM rules for designers to reduce shape variations of the conducting patterns. This offering has been complicating over the rolling-out of new technologies in the past. The complication is most severe with the semiconductor foundries, which manufacture many different designs with the same set of tools. However, not only are the DFM rules an increasing work load, but recent reports also found new manufacturing failures are produced due to the shape changes on the design required by the DFM rules. A new DFM methodology that eliminates such problems is therefore necessary. In this paper, we show how we have achieved DFM in patterning with a significantly simplified set of DFM rules in our sub-100nm technology nodes. We have used photoresist with low activation energy and sensitive PEB properties to achieve high K1 values, and thus eliminating the need of most optical proximity effect driven rules. We also adopt an OPC flow that detects over-varying shapes and automatically performs incremental fix. These technologies simplify the DFM rules and minimize the number of the new problems coming from the traditional DFM method adopted by most foundries. We have achieved better than 90% for various logic and SoC products steadily.

Diagnosis of Optical Lithography Faults With Product Test Sets

Increasing within-die variation, combined with larger numbers of critical and near-critical paths and higher operating frequencies, has increased the sensitivity of chips to path delay faults. A component of within-die variation comes from optical lithography, including the optical proximity effect, lens aberrations, and flare. This paper presents a methodology to generate test sets to diagnose these sources of within-die variation. Specifically, a delay fault diagnosis algorithm is developed to link failing signatures to a set of physical mechanisms originating from lithography. The algorithm relies on layout-dependent timing analysis, path enumeration, test pattern generation, and correlation of pass/fail signatures to diagnose delay faults caused by lithography. The effectiveness of diagnosis is evaluated for ISCAS85 benchmark circuits.

Application of optical proximity correction technology

As process technology scales down to very deep sub-micron (VDSM) in semiconductor manufacturing technology, intrinsic size becomes close to or even shorter than the wavelength used for optical lithography. Thus, some distortions and deformations are introduced by optical proximity effects (OPE) mainly caused by the diffraction and interference of exposure light when layout patterns on a mask are transcribed to a wafer, which influence on the yield and performance of IC circuit. In order to compensate for the deformations, optical proximity correction (OPC) is the most commonly used methodology. Presently, the OPC method is to use a unitary toleration on the whole chip layer, which makes the run time of OPC algorithm longer, causes the size of GDSII files to follow exponential growth, and results in the cost of making mask grow immensely. Firstly, this paper proposes a self-adaptation OPC method with preprocessing function of patterns classification. According to the need of the correction precision, the OPC system divides patterns corrected into two groups with different toleration: critical patterns and general patterns, which enhance the efficiency of the OPC approach. Secondly, a model-based OPC method is presented based on pattern subsection and classification, which keeps the precision of the correction as well as enhances the efficiency. We also propose a rule-based OPC method with general, concise and complete correction rules, and achieve automatic-built rules-based and its looking-up. Thirdly, we also implement an OPC system, called MR-OPC; the MR-OPC system integrates both rule-based OPC and model-based OPC into a whole, so it can solve the confliction between the efficiency and precision. Experimental results show that the MR-OPC system we suggested has advantages of the efficiency and expansibility.

Auxiliary pattern-based optical proximity correction for better printability, timing, and leakage control

Optical proximity correction OPC is a mandatory resolution enhancement technique RET to ensure the printability of layout fea- tures in silicon. The most prominent OPC method, model-based OPC, alters the layout data for the photomask that enables drawn layout fea- tures to be accurately reproduced by lithography and etch processes onto the wafer. This technique in various forms has now become stan- dard in integrated circuit IC manufacturing at 0.18 m and below. How- ever, model-based OPC is computationally expensive and its runtime increases with technology scaling. The cell-based OPC approach im- proves runtime by performing OPC once per cell definition, as opposed to once per cell instantiation in the layout. However, cell-based OPC does not comprehend intercell optical interactions that affect feature printability in a layout context. This leads to printability, and conse- quently, performance and leakage, degradation. In this work, we propose auxiliary pattern-enabled cell-based OPC to improve printability of cell- based OPC, while retaining its runtime advantage. Auxiliary patterns AP are nonfunctional poly features that are added around a standard cell to shield it from optical proximity effects. We present the AP-based OPC approach and demonstrate its advantages over cell-based and model-based OPC in terms of printability as well as timing and leakage variabilities. AP-based OPC improves the edge placement error over cell-based OPC by 68%. To enable effective insertion of AP in cell in- stances at a full-chip layout level, we propose a dynamic programming DP-based method for perturbation of detailed placement. Our approach modifies the detailed placement to allow opportunistic insertion of AP around cell instances in the design layout. By perturbing placement, we achieve 100% AP applicability in designs with placement utilization less than 70%. AP-based OPC also reduces leakage and timing variability compared to conventional cell-based OPC. We further demonstrate that AP insertion achieves timing and leakage variability comparable to that of model-based OPC. © 2008 Society of Photo-Optical Instrumentation Engineers.

Electron beam and optical proximity effect reduction for nanolithography: New results

Proximity effect correction by dose modulation is widely practiced in electron-beam lithography. Optical proximity control is also possible using a combination of shape adjustment and phase control. Assigning “the right” dose (or fill factor and phase for optics) is a well known mathematical inverse problem. Linear programming, by definition, is the appropriate method for determining dose. In the past, the technique was too slow for full-scale implementation in mask making. Here, the authors discuss how recent developments in computer speed and architecture have improved the prospects for full-scale implementation. In addition, the authors discuss some numerical techniques, analogous to gridding and relaxation, that make linear programming more attractive in mask making.

Process Extension Techniques for Optical Lithography: Thermal Treatment, Polarization and Double Patterning

Current 193-nm optical lithography and commercially available 193-nm resists have been pushed far beyond the previously expected critical dimension by using process extension technology for resolution enhancement technology. This paper deals with three kinds of process extension technologies, thermal treatment, polarization, and double patterning. These technologies are modeled and analyzed. If a 50 % pattern shrinkage due to thermal treatment, a 25 % resolution enhancement due to polarization, and a 50 % pattern shrinkage due to double patterning are supposed, an effective combination can generate a sub-50-nm pattern. When the pattern size is smaller, optical proximity effects are more severe. After describing optical proximity effects for each of these technologies, we discuss optical proximity correction methods.

Methodology of Merging Optical-Proximity-Effect Correction with Compensation of Effect of Off-Axis Incidence in Extreme Ultraviolet Lithography

A simulation study proved that an approach of mask pattern correction provided sufficient pattern fidelity on a wafer. The method merges two types of corrections: one for the effects of off-axis incidence on a reflective mask, and the other for optical proximity effects. A simple bias correction to compensate for the effects of off-axis incidence yielded almost the same pattern fidelity for parallel and perpendicular configurations, which describe the relationship between the projection vector of light incident on the mask and the edge of an absorber pattern. In order to determine the appropriate bias, three evaluation functions describing the ratio of the energy for the parallel configuration to that for the perpendicular configuration were considered: the first concerned the energy of rays reflected from a mask, the second concerned the energy of diffracted rays passing through the pupil, and the third concerned 0th-order diffracted rays. The evaluation functions for reflected and 0th-order rays were suitable for comparatively large patterns (line width ≥ 33 nm). The function for diffracted rays passing through the pupil was suitable for relatively small patterns (line width = 22 nm). Since simply biased mask patterns produce the same pattern fidelity irrespective of the configuration, it is possible to apply conventional methods of optical-proximity-effect correction to the absorber patterns on a reflective mask. A comb pattern was used to demonstrate the feasibility of merging the two types of corrections.

Restricted Optical Proximity Effect Correction Pattern Generation Based on Optical Proximity Effect Correction-Design for Manufacturability Rule in Model-Based Optical Proximity Effect Correction: Application for Metal Layer in Complementary Metal–Oxide–Semiconductor Logic Process

In the recent submicron technologies, the pattern formation on photomasks is increasing in its difficulty owing to the complexity of optical proximity effect correction (OPC) and resolution enhancement techniques (RET). The detection and repair of critical patterns after OPC or RET have become essential procedures for photomask preparation, and design rule check (DRC) or lithography simulation tools have often been used to verify these patterns. However, the detection and repair of critical patterns have been becoming an excessive burden in the development of lithography processes and mask data processing. In this paper, we describe how to detect and repair these OPC critical patterns in lithography using the OPC-DFM rule, which can be derived from the OPC extraction test element group (TEG) effectively and easily. This technology enables the removal of OPC critical patterns before photomask preparation.

Backend dielectric breakdown dependence on linewidth and pattern density

Time-dependent dielectric breakdown of copper/low- k interconnects has been found to degrade for narrow metal lines. Several feasible causes for degradation have been investigated, including enhanced electric fields, the optical proximity effect, and microloading in etch. Microloading is found to be the best explanation of the observed behavior. A mathematical model has been developed to relate the geometries of layout features to mean-time-to-failure (MTTF).

Automated hot-spot fixing system applied to the metal layers of <inline-formula><math altimg="none" display="inline" overflow="scroll"><mrow><mn>65</mn><mtext>-</mtext><mi>nm</mi></mrow></math></inline-formula> logic devices

Hot-spot clearance using process simulation is indispensable for low-k1 lithography processes. Hot spots will occur mainly depending on local pattern context. Appropriate calibration of design rules, mask data preparation, resolution enhancement techniques, and optical proximity effect correction will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of the design at the hot spot will be effective, but it takes too much time. Therefore, there is a need for an automated hot-spot fixing system so as to avoid fatal hot-spot occurrence, with sufficient process margins and short turnaround time. We developed an automated hot-spot fixing system, the hot-spot fixer (HSF). Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. We applied the HSF system to the metal layer of logic devices of 65 nm and most of the hot spots were diminished throughout a full chip within 12 hours. Thus, HSF feasibility has been proved for metal layers in the 65-nm node and below with full-chip data volume.

Thermal treatment for optical proximity correction

For 32-nm technology node, thermal treatment is one of the process extension techniques with 193-nm ArF lithography equipment and chemically-amplified resist (CAR). However, it is difficult to use these techniques in the manufacture process because the optical proximity effect of thermal effects is quite severe. In this paper, thermal processes, such as softbake, post-exposure bake and thermal reflow, are described and modeled to investigate the property changes of a positive type, 193-nm CAR. The simulated results agree well with the experimental results. For the optical proximity correction (OPC) of the thermal effects, an orthogonal functional method is introduced. Due to contact hole (C/H) pattern, the underbake of post-exposure bake (PEB) and thermal reflow are performed for the 45-nm critical dimension (CD) by using the OPC simulated images, to demonstrate the possibility of controlling these thermal processes for the formation of 32-nm CD.

Mask Cost and Profitability in Photomask Manufacturing: An Empirical Analysis

An empirical study of the economics of manufacturing photomasks concludes that the uncontrolled growth of optical proximity effect correction and resolution enhancement techniques is driving up the cost of pattern generation and mask inspection to levels that threaten the profitability of photomask manufacturing. The intrinsic cost of some leading edge photomasks has already exceeded the price that customers are willing to pay for them. A model of the lifecycle of photomask manufacturing, developed from interviews involving the 1990-to-2005 operations of six mask shops and a survey of seven photomask manufacturers, shows that design for manufacturability (DFM) constitutes the most promising approach for alleviating this market impasse. Unilateral action by mask shops to increase their capital productivity is necessary but insufficient and perhaps unaffordable. DFM solutions will require the majority of participants in the lithography value chain to collaborate according to a volatile demand schedule that is driven by semiconductor manufacturers

Model-Based Optical Proximity Correction for Resist Reflow Process

For the patterning of sub-100 nm contact holes, thermal reflow is suggested as a good method of resolving the cost problems of resolution-enhancement technology and the new lithography technology. However, it is difficult to use this process in lithography process because the optical proximity effect of thermal reflow is quite severe. In this study, the optical proximity effects before and after thermal reflow are described. Resist reflow is modeled and simulated for a top-view image. For repeated contacts and random contacts, thermal reflow biases are modeled and compensated for pattern arrays. Simulation results agree well with the experiment results in a small error range according to baking temperature, time, and pitch size. For the optical proximity correction of thermal reflow, two-stage corrections, and model-based optical proximity corrections before and after thermal reflow, are described. The model-based optical proximity correction before thermal reflow can be required using pull-simulated images rather than an aerial image as pattern critical dimension shrinks down to sub-100 nm. The possibility of thermal reflow for the formation of a sub-100 nm pattern is shown by simulating a model-based optical proximity correction of a 45 nm contact hole.

Characteristics of ArF Immersion Lithography Using Topcoat

This paper is intended as investigations of two interesting characteristics of ArF immersion lithography using topcoat (TC). On the one hand, we identified several hundreds gel-type defects over large areas of the unexposed top surface of the resist in cases where a TC was used. On the other hand, we observed that the optical proximity effect (OPE) profiles in immersion lithography varied with the type of TC materials beyond expectation. The magnitude of OPE was reduced to approximately 20 nm in the region of maximum influence. We investigated the influences on these characteristics of the TC material and the methods of application (i.e. baking conditions and exposure). The chemical interaction (e.g., mixing) between the resist and the TC was examined by employing time-of-flight mass spectrometry with gradient shaving preparation (GSP + TOF) and FT-IR measurements and by focusing on the interface of the resist and TC. We confirmed consistent correlations between lithographic properties and chemical interaction. The TC material and process which form much mixing layer due to the chemical interaction tended to cause gel-type defect and variation of OPE profile.

Low loss silicon on insulator photonic crystal waveguides made by 193nm optical lithography

We show the successful fabrication and operation of photonic crystal waveguides on SOI, with lower silicon dioxide cladding remaining, using 193 nm DUV lithography. We demonstrate that 193 nm lithography gives more process latitude, allowing a wider range of periods and hole diameters to be printed, as well as reducing the optical proximity effect to a minimum. The smallest period /hole size variation printed successfully was 280 nm and 150 nm, which is very promising for ambitious future designs. Lowest losses obtained were 14.2 +/- 2.0 dB/cm for a W1 waveguide in a 400 nm lattice with an r/a of 0.25 at a frequency of 0.257 a/lambda, which approaches the best losses reported for air-bridge type W1s.

Mask Pattern Correction by Energy Loss Compensation in Extreme Ultraviolet Lithography

In extreme ultraviolet (EUV) lithography with off-axis incidence, the incident light loses energy when it is reflected from a mask onto a wafer because the absorber pattern blocks some of the incident and diffracted light, and the absorber side wall reflects some of the incident light. This study concerns mask pattern correction to compensate for the energy loss at the pupil. Simple negative biasing was found to be an effective compensation technique. That is, when the absorber stack is thin, a narrowed mask pattern by adding a negative bias and off-axis incidence produce about the same optical proximity effects (OPE) as an unbiased mask and normal incidence. This makes it possible to use conventional algorithms for optical proximity effect correction (OPC), which are optimized for normal incidence. For a thin absorber stack, combining energy loss compensation for off-axis incidence with conventional OPC for normal incidence provides excellent pattern fidelity, sufficient critical dimension (CD) uniformity, and good pattern edge contrast at the same time.