Optical Proximity Correction Techniques Research Articles

The study of lithographic variation in resistive random access memory

Reducing the process variation is a significant concern for resistive random access memory (RRAM). Due to its ultra-high integration density, RRAM arrays are prone to lithographic variation during the lithography process, introducing electrical variation among different RRAM devices. In this work, an optical physical verification methodology for the RRAM array is developed, and the effects of different layout parameters on important electrical characteristics are systematically investigated. The results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography environments. The read resistance is more sensitive to the locations in the array (~30%) than SET/RESET voltage (<10%). The increase in the RRAM device length and the application of the optical proximity correction technique can help to reduce the variation to less than 10%, whereas it reduces RRAM read resistance by 4×, resulting in a higher power and area consumption. As such, we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.

Machine Learning based Optical Proximity Correction Techniques

Machine Learning based Optical Proximity Correction Techniques

Fast optical proximity correction method based on nonlinear compressive sensing.

Optical proximity correction (OPC) is an extensively used resolution enhancement technique (RET) in optical lithography. To date, the computational efficiency has become a big issue for pixelated OPC techniques due to the increasing complexity of lithographic masks in modern integrated circuits. This paper is the first to apply nonlinear compressive sensing (CS) theory to break through the computational efficiency of gradient-based pixelated OPC methods. The proposed method reduces the dimensionality of the OPC problem by downsampling the layout pattern. Then, a nonlinear cost function is established to guarantee the lithography imaging performance on the downsampled layout. Under the sparsity assumption of the mask, the OPC problem is formulated as an inverse nonlinear CS reconstruction problem. The iterative hard thresholding (IHT) algorithm is then used to solve for the OPC problem. The proposed method proves to improve the computational efficiency of traditional gradient-based OPC methods, while improving the process windows of the lithography systems. Benefiting from the sparse property of the mask patterns, the mask manufacturability can also be improved compared to traditional methods.

Intelligent optical proximity correction using genetic algorithm with model- and rule-based approaches

Optical lithography is one of the key technologies in semiconductor material and device fabrications. It is a process to transfer the layouts of desired pattern onto the wafers. However, the exposure on wafer has distortions due to the proximity effects. As the minimum feature sizes of explored samples continue to shrink, the mismatch between the pattern and the experimental result on wafer is significant. Corrections of mask patterns between the sample and post exposure result are thus necessary. Optical proximity correction (OPC) is the process of modifying the geometries of the layouts to compensate for the non-ideal properties of the lithography process. Given the shapes desired on the wafer, the mask is modified to improve the reproduction of the critical geometry. In this work, we propose an intelligent OPC technique for process distortion compensation of layout mask. To perform the mask correction in sub-wavelength era, two different strategies including the genetic algorithm (GA) with model-based OPC and the GA with rule-based OPC methods are examined. The proposed intelligent system consists of three parts: the preprocess, the OPC engine, and the post-process. During the pre-process, the pattern analyzer will analysis all patterns and then divided them into many segments for model-based OPC or generates assistant patterns for rule-based OPC. Secondly, the OPC module is applied to correct the mask. The intelligent module searches the whole problem domain to find out the best combination of the mask shape by the GA. The corrected mask is verified by performing lithographic simulation to get the error norm between exposed result and desired layout. Finally, the mask verification is conducted in the post-process. By testing on several fundamental patterns, this approach shows good correction accuracy and efficiency, compared with experimentally fabricated samples. It can be applied to perform the mask correction in sub-wavelength era.

Design freedom gets the brush-off [chip design

Various techniques have been used to push processes this far past the point where diffraction effects kick in. These have included using phase-shift masking to turn diffraction to the designers' advantage, and optical proximity correction (OPC) techniques, such as adding 'ears' to the corners of layout elements so that they are printed as right angles. The problem is that chipmakers are applying ever more Byzantine combinations of these techniques to keep up with shrinking process dimensions, and getting diminishing returns. Device characteristics are varying wildly as more aggressive OPC techniques are pressed into action. The chip equipment industry has been working to solve this for years, but couldn't persuade its customers that moving to 157nm illumination sources was worth the development costs given the marginal advantages it would bring over 193nm light. Unfortunately, the development of EUV lithography is fraught with difficulties. The solution to the 65 nm and 45 nm design for manufacture is new DFM routers. As they are DFM-aware they can run the rule-based checks and ensure that around 80 percent of the DFM problems are avoided. The layout team can then use model- based DFM to take care of the remaining 20 percent.

Optical Proximity Correction using an Optimization Method after Layout Design

This paper proposes an optical proximity correction (OPC) using an Adjustable OPCed cell and genetic algorithms (GA) to achieve optimal OPC feature generation for the full-chip area at fast processing speeds. GA is an efficient optimization technique based on population genetics. In this approach, an Adjustable OPCed cell consists of two parts. The first part is the “fixed area”, which includes OPC feature data from a conventional OPC technique. The second part is the “adjustable area”, which is located in the peripheral regions of the cell and includes adjustable OPC variables. As the values of these variables are greatly influenced by neighboring cell patterns, the variables are quickly optimized by the GA after cell layout. The effectiveness of this approach, in terms of reduced times for accurate simulations and repeated modification of OPCed features, is demonstrated through computational experiments.

Tricks of the light [optical lithography

Physical IC design keeps getting more difficult as efforts to extend optical lithography beyond the 65nm generation impose limits on layouts. Process engineers have decided that they are stuck with the type of ultraviolet light that they use today in chipmaking for at least the next couple of generations of chip technology. The 193nm wavelength appeared with the 90nm process just as research on 157nm wound up because of problems with lenses and resists. That means the wavelength of light used to draw features on a chip is several times larger than the features themselves. As minimum process dimensions have shrunk to even smaller fractions of the illumination wavelength, various post-layout optimizations have been introduced to compensate for diffraction effects that result. Optical proximity correction techniques ensure that very closely spaced layout features can be formed on the wafer, by taking account of the way that light patterning one feature interferes with light patterning its neighbor. These corrections have been joined by other resolution enhancement techniques that continue to put pressure on designers to conform to increasingly complicated rules. At the same time, the techniques make the relationship between the original layout and what appears on the wafer less certain.

Shape engineering: A novel optical proximity correction technique for attenuated phase-shift mask

Modifications of the shapes and relative orientations of contact windows in attenuated phase shifting mask are studied theoretically and experimentally to maximize process latitude and resolution and to minimize sidelobe printability. By utilizing a non-square contact window shape and maintaining the overall pattern transmission, we achieve considerable sidelobe suppression with no loss in process latitude and resolution.

Proximity Effects Correction for Advanced Optical Lithography Processes

This paper describes the performance of various optical proximity correction (OPC) software packages in terms of correction accuracy and effectiveness. Although parts of these software packages have been made commercially available couple of years ago, their performance keeps improving by the new features and capabilities added continuously in time by the software vendors. In this study we address mainly the lithographic performance of the OPC techniques implemented in the software packages, including many of the new features which are still in a development phase. Corrections using one of these software packages were carried out for an advanced sub-0.3 µm i-line process after poly-Si etching. Corrections for an advanced 0.2 µm deep-UV process were carried out using two other OPC software packages, representing two different OPC techniques. Exposures were carried out on state-of-the-art i-line and deep-UV steppers equipped with high numerical aperture lenses and illuminators allowing the user to vary the coherence factor by keyboard control. Optimized optical settings towards reducing optical proximity effects have been used. Results on the effectiveness of reducing linewidth variation and line-end shortening for various pitches using these OPC techniques are reported.

Optical proximity correction: A detail comparison of techniques and their effectiveness

The study presented here quantifies the benefit of optical proximity correction (OPC) for an I-line and a DUV wafer process in a systematic way. Masks and wafers made with 6 mask writing techniques and 5 OPC software packages each with 6 degrees of aggressiveness were studied. The benefits for 1-D corrections (isolated/dense bias), 1.5-D effects (line end pullback), and 2-D effects (corner rounding) were evaluted. From the accumulated data in the study, we can conclude that OPC features deliver significantly improved line width uniformity and pattern fidelity to etched wafers. The technology is effective and manufacturable with contemporary mask writers and OPC techniques. Data expansion and mask inspection difficulty factors were also investigated.

Challenges for 0.35-0.25 μm optical lithography

Lithography has enabled the continuous shrinking of device geometry over many years. Whereas it has been predicted many times that optical lithography would run out of steam, it still is the technology of choice, and this will certainly remain for a considerable time. Traditionally, this scaling has been made possible by using lower wavelength light sources and higher numerical aperture projection lenses. It is generally believed that i-line will be the mainstream technology for 0.35 μm lithography, while DUV (248 nm) will be needed for 0.25 μm. During the last years, various resolution enhancement techniques, such as phase shifting masks, off-axis illumination and surface imaging have been proposed. Very often, these techniques have been optimized to reduce the depth-of-focus loss, which is unavoidable using the lower wavelengths and higher numerical apertures. In this paper the current challenges for printing 0.35-0.25 μm dimensions will be reviewed. Although the mainstream technologies for 0.35 and 0.25 μm are more or less settled, the main challenge will most likely be critical dimension (CD) control. Optical proximity effects and substrate reflections start to play a major role in the CD budget. Methods to overcome these problems are obviously optical proximity correction techniques and the use of anti-reflective coatings and surface imaging. Moreover, a lot of gain can be obtained from reoptimizing current processes for maximum exposure latitude, combined with the minimally required focus budget. It will be shown that optimization of the lithography process (stepper parameters, mask, illumination, resist process) towards CD control results in different conclusions than optimization towards maximum depth-of-focus (DOF). Furthermore, a practical example of 0.25 μm lithography, using the combination of attenuated PSM and off-axis illumination, will be given. In an attempt to indicate the future of optical lithography, a simulation study is presented which starts from this example. Reasonable processing windows are obtained down to 0.12 μm by using ‘known’ techniques.