Optical Proximity Correction Recipe Research Articles

Layout pattern analysis and coverage evaluation in computational lithography.

In advanced semiconductor technology nodes, the model accuracy of optical proximity correction (OPC) is the key for integrated circuit (IC) chip mask tape out, yield ramp up, and product time-to-market. An accurate model means a small prediction error for the full chip layout. As the full chip layout usually has large pattern variety, an optimal pattern set with good coverage is desired during the model calibration process. Currently, no existing solutions can provide the effective metrics to evaluate the coverage sufficiency of the selected pattern set before a real mask tape out, which may potentially cause higher re-tape out cost and product time-to-market delay due to the multiple rounds of model calibration. In this paper, we construct the metrics to evaluate the pattern coverage before any metrology data is obtained. The metrics are based on either the pattern's intrinsic, numerical feature representation, or its potential model simulation behavior. Experimental results show a positive correlation between these metrics and lithographic model accuracy. An incremental selection method is also proposed based on the pattern simulation error. It reduces up to 53% of the model's verification error range. These pattern coverage evaluation methods can improve the efficiency of OPC model building, and are, in turn, beneficial to the whole OPC recipe development process.

LRC Based OPC Recipe Qualification

Typical IC layouts are simple shapes such as rectangles and 45 degree triangles. However, the high-spatial-frequency components of the mask spectrum cut off by the low-pass pupil will result in the rounded images and pattern distortions. Although optical proximity correction (OPC) has been proposed to address this issue as a standard industry practice, there are no theoretically perfect corrections due to some physical or chemical limitations. Therefore, how to qualify the correction results has become a problem. In this paper, the lithography rule check (LRC) based OPC recipe qualification is proposed. By extracting and grouping the LRC databases, the point-to-point post-OPC comparison matrix is shown. Finally, this new methodology can be integrated into the regression flow. When changing to a new software version or different OPC flow, this new validation methodology can not only tell the differences, but also report if there are any OPC quality degradations.

Transferring optical proximity correction effects into a process model

Because of the ever-decreasing feature size in modern photolithography, the complexity of semiconductor patterns continues to increase dramatically, resulting in prolonged tape-out times. The most time-consuming process in the tape-out flow is model-based optical proximity correction (OPC), which employs two components: a process model and a recipe. The process model predicts how the manufacturing process will behave at a given location on a wafer, whereas the recipe controls how the model information is used to modify the pattern. The recipe uses the model multiple times for each fraction of a polygon in a semiconductor device pattern, resulting in hundreds of billions of complex and time-consuming calculations. To analyze a design-team-drawn device pattern for semiconductor manufacturability, these tape-out calculations need to be performed. This study is designed to reduce the semiconductor pattern manufacturing analysis time by creating an OPC recipe simulation in the process model for use in rapid analysis and filtering of the drawn semiconductor design. In this study, the authors introduce a method of calculating the OPC effect by modifying the optical model, which is equivalent to transferring the OPC effect into the process model.

From 120 to 32 nm CMOS technology: development of OPC and RET to rescue optical lithography

Starting from the 120 nm CMOS technology node down to the 32 nm node, we have entered into a new lithographic regime. The wavelength has not changed (only 193 nm), and we move closer and closer to the theoretical optical resolution limit. Therefore, Resolution Enhancement Techniques (RET) have been developed in order to print all shapes properly and close the resolution gap. The primary RET developed are off-axis illumination, sub-resolution assist features and a phase shift mask. Moreover, working closer to the resolution limit implies bigger image distortion between the mask and the silicon. For this purpose OPC (Optical Proximity Correction) has been widely used by making mask pre-compensation of all non linear effects, optical diffraction and interference effects, resist and etch. RET and OPC are also fundamentally linked. RET such as off-axis illumination generates more distortion, and therefore justifies the need of more aggressive OPC, and RET techniques like Alt PSM and sub-resolution assist features are generated through the OPC infrastructure. From its first industrial utilization for 120 nm node to 32 nm prospectively, many evolutions have been seen for OPC. These include the generalisation to all lithographic layers, moving to pixel based simulation, usage of full chip simulation and verification, the incorporation of process window effects like Energy Latitude or Depth of Focus into the OPC algorithm, and inverse lithography approach. For RET, we have seen huge differentiation depending on the type of application, such as logic or memory. In conclusion, we need to consider design as a third party that is playing a key role in this RET–OPC synergy. To use more aggressive RET and reduce the cycle time of OPC recipe development, more regular designs are considered as a key enabler for the future: they will allow logic makers to consider RET options that are pushed as far as those used by memory makers. To cite this article: Y. Trouiller, C. R. Physique 7 (2006).