Optical Overlay Metrology Research Articles

Computational vibration mitigation using phase interpolation in digital holographic microscopy for overlay metrology.

Digital holographic microscopy retrieves amplitude and phase information of an image which allows us to computationally correct for imperfections in the imaging optics. However, digital holographic microscopy is an interferometric technique that is inherently sensitive to undesired phase variations between object and reference beam. These phase variations lower the fringe contrast if they are integrated over a finite exposure time which leads to a reduced amplitude of the retrieved image. This results in significant errors in applications that rely on a stable and accurate amplitude measurement, such as optical overlay metrology in the semiconductor industry. We present experimental results on a computational vibration mitigation method for the application of overlay metrology using phase interpolation between a sequence of measured holograms and demonstrate its capability to improve metrology precision in an overlay metrology application that uses digital holographic microscopy.

Aberration calibration and correction with nano-scatterers in digital holographic microscopy for semiconductor metrology.

Overlay metrology measures pattern placement between two layers in a semiconductor chip. The continuous shrinking of device dimensions drives the need to explore novel optical overlay metrology concepts that can address many of the existing metrology challenges. We present a compact dark-field digital holographic microscope that uses only a single imaging lens. Our microscope offers several features that are beneficial for overlay metrology, like a large wavelength range. However, imaging with a single lens results in highly aberrated images. In this work, we present an aberration calibration and correction method using nano-sized point scatterers on a silicon substrate. Computational imaging techniques are used to recover the full wavefront error, and we use this to correct for the lens aberrations. We present measured data to verify the calibration method and we discuss potential calibration error sources that must be considered. A comparison with a ZEMAX calculation is also presented to evaluate the performance of the presented method.

Diffraction-based overlay metrology using angular-multiplexed acquisition of dark-field digital holograms.

In semiconductor device manufacturing, optical overlay metrology measures pattern placement between two layers in a chip with sub-nm precision. Continuous improvements in overlay metrology are needed to keep up with shrinking device dimensions in modern chips. We present first overlay metrology results using a novel off-axis dark-field digital holographic microscopy concept that acquires multiple holograms in parallel by angular multiplexing. We show that this concept reduces the impact of source intensity fluctuations on the noise in the measured overlay. With our setup we achieved an overlay reproducibility of 0.13 nm and measurements on overlay targets with known programmed overlay values showed good linearity of R2= 0.9993. Our data show potential for significant improvement and that digital holographic microscopy is a promising technique for future overlay metrology tools.

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.

Critical dimension scanning electron microscope local overlay measurement and its application for double patterning of complex shapes

We have developed a new local overlay measurement technique on actual device patterns using a critical dimension scanning electron microscope (CD-SEM), which can be applied to two-dimensional (2D) device structures such as a static random access memory contact hole array. CD-SEM overlay measurement can provide additional local overlay information at the site of device patterns, complementary to the optical overlay. The methodology includes the use of pattern symmetry to cancel out many process effects and reduce measurement uncertainty. CD-SEM overlay metrology was compared with conventional optical overlay metrology in terms of measurement uncertainty and overlay model analysis, and very good correlation was confirmed. The developed methodology was applied to local overlay measurement of double patterning contact hole layers of leading edge devices. The local overlay distribution was obtained across the device area, and spatial correlation of the overlay error vectors was examined over a large range of distances. The applications of CD-SEM overlay metrology were explored, and methodologies were introduced to examine both the overlay of double patterning contacts at the edge of an array and lithographic process-induced overlay shift of contacts. Finally, a hybrid optical CD-SEM overlay metrology was introduced in order to capture a high order, device weighted overlay response.

Effects of illumination wavelength on the accuracy of optical overlay metrology

As the integration density in the manufacturing of IC's increases and tighter design rules are implemented, the accuracy of overlay in the photolithography process is becoming all the more important. Consequently, investigation and characterization of the accuracy (as well as precision) of the overlay measurement are being required to insure that the overlay metrology tool qualifies for the new technologies. In this paper, we analyze the relationship between wafer substrate types and the respective characteristic overlay measurement errors associated with them. We compare results using different illumination wavelengths in the overlay tool. We define the Wafer Induced Shift (WIS) contribution to the measurement accuracy error and introduce a metric for it. And we analyze the relationship between the TIS and WIS. We show that the wavelength of the optical overlay measurement (OL, for short) should be fitted separately to each of the various kinds of overlay measurement targets, or marks. Buried type targets, covered by transparent materials, for which the measurement is made through the transparent interlayer, benefit from wavelength selection due to the possible improvement in contrast associated with an interference effect. Open type targets, on the other hand, in which the measurement signal is collected off the substrate shape itself, do not benefit from that. There is another problem to consider, however. Such targets may show a considerable WIS, even thought TIS and precision are good both before and after etch. The WIS error can be as high as 100 nm. This could create serious OL problem and it means that TIS and precision are not enough to characterize the quality of measurement, and WIS is equally important, it not more so. We look into the causes of WIS in the substrate shape, overlay mark design and fabrication method. We show that with careful selection of illumination wavelength, some layers produce no WIS. On the other layers WIS remains a problem and other methods are still required to control it.

Recent Developments in Electrical Linewidth and Overlay Metrology for Integrated Circuit Fabrication Processes

Electrical linewidth measurements have been extracted from test structures replicated in planar films of monocrystalline silicon that were electrically insulated from the bulk-silicon substrate by a layer of silicon dioxide formed by separation by the implantation of oxygen (SIMOX) processing. Appropriate selection of the surface orientation of the starting material, the design and orientation of the structure's features, and patterning by a lattice-plane selective etch provide features with planar, atomically smooth sidewalls and rectangular cross sections. The primary motivation for this approach is to attempt to overcome the serious challenge posed by methods divergence to the certification of linewidth reference-materials for critical-dimension (CD) instrument calibration and related tasks. To enhance the physical robustness of reference features with deep submicrometer linewidths, the new test structure embodies short reference-segment lengths and arbitrarily wide voltage taps. Facilities for reconciliation of measurements extracted from the same feature by all normally practiced techniques are also implemented. In overlay metrology, electrical inspection of two types of hybrid overlay targets allows pixel calibration of, and shift extraction from, the overlay instruments. The overall strategic focus of this research is to resolve methods-divergence issues and possibly to develop universal deep-submicrometer linewidth reference materials for CD instruments and techniques for instrument- and process-specific shift extraction for optical overlay metrology.