Optical Network-on-chip Research Articles

A Survey of On-Chip Optical Interconnects

Numerous challenges present themselves when scaling traditional on-chip electrical networks to large manycore processors. Some of these challenges include high latency, limitations on bandwidth, and power consumption. Researchers have therefore been looking for alternatives. As a result, on-chip nanophotonics has emerged as a strong substitute for traditional electrical NoCs. As of 2017, on-chip optical networks have moved out of textbooks and found commercial applicability in short-haul networks such as links between servers on the same rack or between two components on the motherboard. It is widely acknowledged that in the near future, optical technologies will move beyond research prototypes and find their way into the chip. Optical networks already feature in the roadmaps of major processor manufacturers and most on-chip optical devices are beginning to show signs of maturity. This article is designed to provide a survey of on-chip optical technologies covering the basic physics underlying the operation of optical technologies, optical devices, popular architectures, power reduction techniques, and applications. The aim of this survey article is to start from the fundamental concepts and move on to the latest in the field of on-chip optical interconnects.

An Algorithmic Framework to Construct Optical Switch via Scaling From N-to-2N Ports for Optical Network on Chip

Optical network-on-chip (ONoC), designed with non-blocking optical switches, is gaining a significant research attention to meet the upcoming requirements of higher throughput, larger bandwidth, lower latency, and reduced power consumption for manycore processors. In this paper, we propose an algorithmic framework to construct non-blocking optical switches with multiple interconnection possibilities. The design is accomplished by scaling the optical switch from N-to-2N ports using two intermediate mapping matrices each of size 2N × 2N. These mapping matrices are the row and column permutations of identity matrices, where 1's represent passive interconnections among the optical switching units (OSUs). The proposed framework provides validation to the design by identifying all the non-blocking permutations of the mapping matrices, thereby, providing a flexibility to adopt any permutation as an interconnection scheme. Furthermore, it has the ability to quantify the redundancy in switching combinations which exists for any input-to-output routing, authenticates the non-blocking feature of the optical switch and to reduce the number of optical switching units while preserving the non-blocking characteristic. For the scaled 4 × 4 and 6×6 optical switches, we respectively identified 16 and 192 different interconnections to build multiple non-blocking switches. Moreover, a 20% reduction in OSUs is achieved by optimizing a 6 × 6 switch. The influence of the insertion loss, power consumption, and crosstalk noise on various scaled optical switch networks are also analyzed and compared with several existing optical switch topologies.

On-Chip Hardware Accelerator for Automated Diagnosis Through Human–Machine Interactions in Healthcare Delivery

The automated diagnosis helps us better understand the complex landscape of diseases, leading to more effective, early and reliable medical diagnosis and therapy. The human–machine interactions in healthcare delivery relying on automated cyber-physical systems (ACPSs) play an important role in the automated diagnosis. Currently, the multicore accelerator used for ACPS has utilized the network-on-chip (NoC) for personalized healthcare. However, the discrete cores based on NoC are affected by limited computation speed, since the data have to pass through an electrical interconnect. In this paper, we propose a novel optical NoC (ONoC) solution of designing discrete cores to quickly understand biomarkers for early detecting abnormal pathophysiology, such as the deviation from the protein’s native state. We analyze the performance of our ONoC-based ACPS accelerator for personalized healthcare by virtue of the tested proteins widely adopted in the lattice protein model. Our mathematical analysis and simulation results demonstrate that: 1) the chip area becomes smaller than a traditional design, which makes the personalized healthcare product more convenient; 2) the computation speed is promoted, resulting in the rapid understanding of biomarkers; and 3) we improve the data transmission reliability through accurately capturing the photonic effect so that desirable human–machine interactions can be guaranteed. Note to Practitioners —We design an on-chip hardware accelerator for automated diagnosis and personalized healthcare by predicting biological protein folding. The simulation results based on the lattice protein model can well guide the practitioners to design a more convenient and reliable product quickly detecting the biomarker, such as the deviation from the protein’s native state.

Layout optimization methodology for ring-based on-chip optical network

Layout optimization methodology for ring-based on-chip optical network

An Low-Power Area-Efficient Routing Analysis and Optimization for a Fat Tree-Based Optical Network-on-Chip (ONoC) Architectures

An Low-Power Area-Efficient Routing Analysis and Optimization for a Fat Tree-Based Optical Network-on-Chip (ONoC) Architectures

A large-scale nesting ring multi-chip architecture for manycore processor systems

The optical network on chip (ONoC) paradigm has emerged as a promising solution to multi-core/many-core processor systems for offering enormous bandwidth and low power consumption. As chip multiprocessors (CMPs) scale to unprecedented numbers of cores, the performance of next-generation CMPs will be bounded by the process yield and power density of single chip. In earlier work we proposed a multi-chip ONoC architecture that scales to large numbers of CMPs and delivers high performance in terms of delay and throughout. Building on that work, in this paper we propose an optimized architecture for integrating a large number of cores into chips with a novel control strategy, including a contention resolution scheme and a resource reservation scheme. The proposed control strategy is crucial to large scale ONoCs, because the resource reservation scheme ensures efficient wavelength allocation for the traffic while the contention management scheme is effective in reducing the impact of contentions. To sustain good performance and energy efficiency of large-scale ONoC, the topology is optimized to reduce the average transmission distance with minimum increase of power consumption. We evaluate the proposed architecture within a 1000-core processor system and compare it with CMesh and several previously proposed topologies with different control strategies. The simulation results show that, our new large-scale architecture can achieve better performance on throughput and delay.

Ultrasmall in-plane demultiplexer enabled by an arrayed one-dimensional photonic crystal nanobeam cavity

We propose a design for silicon-on-chip integrated eight-channel wavelength division multiplexing (WDM) demultiplexer, which consists of parallel-arrayed one-dimensional (1-D) photonic crystal nanobeam cavities (PCNCs) with high-Q over 105 and large free spectral range of ∼200 nm. To the best of our knowledge, this is for the first time that a 1-D PCNC-based demultiplexer is presented. The performance of the device is investigated theoretically by using three-dimensional finite-difference time-domain method. To enable eight-channel parallel arrayed 1-D PCNCs to be coupled to on-chip optical networks for higher integration and multiplex application, an 1 × 8 taper-type equal optical power splitter is used to connect all channels simultaneously. The total device footprint is as small as 12 μm × 15 μm (width × length), which is decreased by five times compared to that per channel in the recent two-dimensional (2-D) PC-based demultiplexer. Moreover, the average channel spacing smaller than 115 GHz is achieved, which is more than two times smaller than that of 2-D PC nanocavity devices, demonstrating that the arrayed nanocavities have the potential for developing ultracompact 100-GHz spaced filters in a dense WDM system. Thus, we believe that the results demonstrated in this work is promising for the future on-chip photonics integrated circuits and optical communication systems.

On-chip reconfigurable and scalable optical mode multiplexer/demultiplexer based on three-waveguide-coupling structure.

Reconfigurable optical mode multiplexers/demultiplexers have attracted increasing attention in the academic community, because they enable convenient construction of flexible and complex on-chip optical networks. Here, we propose and demonstrate a scheme of reconfigurable and scalable optical mode multiplexer/demultiplexer with large operation bandwidth, based on three-waveguide-coupling structures. As proof of concept, a reconfigurable device that can multiplex input signals to the fundamental and first-order quasi-transverse electric mode is fully fabricated and demonstrated successfully. Static response spectra show that the optical crosstalk at the output ports of the device are less than -14.3 dB and -13.7 dB over the entire C band (> 40 nm), respectively. The dynamic performance with data transmission speeds of 40 Gbps for each multiplexing channel are also demonstrated successfully. The presented device is believed to be a potential candidate for future on-chip optical network with large-scale integration, flexible functionality, and low cost.

Bufferless Transmission in Complex Networks

Complex bufferless networks such as on-chip networks and optical burst switching networks have not been paid enough attention in network science. In complex bufferless networks, the store and forward mechanism is not applicable, since the network nodes are not allowed to buffer data packets. In this brief, we study the data transmission process in complex bufferless networks from the perspective of network science. Specifically, we use the Price model to generate the underlying network topological structures. We propose a delivery queue based deflection mechanism, which accompanies the efficient routing protocol, to transmit data packets in bufferless networks. We investigate the average deflection times, packets loss rate, average arrival time, and how the network topological structure and some other factors affect these transmission performances. This brief provides some clues for the architecture and routing design of bufferless networks.

A Learning-Based Thermal-Sensitive Power Optimization Approach for Optical NoCs

Optical networks-on-chip (NoCs) based on silicon photonics have been proposed as emerging on-chip communication architectures for chip multiprocessors with large core counts. However, due to the thermal sensitivity of optical devices used in optical NoCs, on-chip temperature variations cause significant thermal-induced optical power loss, which would counteract the power advantages of optical NoCs. To tackle this problem, in this work, we propose a learning-based thermal-sensitive power optimization approach for mesh- or torus-based optical NoCs in the presence of temperature variations. The key techniques proposed include an initial device-setting and thermal-tuning mechanism that is a device-level optimization technique, and a learning-based thermal-sensitive adaptive routing algorithm that is a network-level optimization technique. Simulation results of an 8x8 mesh-based optical NoC show that the proposed initial device-setting and thermal-tuning mechanism confines the worst-case thermal-induced optical energy consumption to be on the order of tens of pJ/bit, by avoiding significant thermal-induced optical power loss caused by temperature-dependent wavelength shifts. Besides, it shows that the learning-based thermal-sensitive adaptive routing algorithm is able to find an optimal path with the minimum estimated thermal-induced optical power consumption for each communication pair. The proposed routing has a greater space for optimization, especially for applications with more long-distance traffic.

Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects

Optical Network-on-Chip (ONoC) is a promising communication medium for large-scale multiprocessor systems-on-chips. Indeed, ONoC can outperform classical electrical NoCs in terms of energy efficiency and bandwidth density, in particular, because this medium can support multiple transactions at the same time on different wavelengths by using Wavelength Division Multiplexing (WDM). However, multiple signals sharing simultaneously the same part of a waveguide can lead to inter-channel crosstalk noise. This problem impacts the signal-to-noise ratio of the optical signals, which leads to an increase in the Bit Error Rate (BER) at the receiver side. If a specific BER is targeted, an increase of laser power should be necessary to satisfy the SNR. In this context, an important issue is to evaluate the laser power needed to satisfy the various desired communication bandwidths based on the BER performance requirements. In this article, we propose an off-line approach that concurrently optimizes the laser power scaling and execution time of a global application. A set of different levels of power is introduced for each laser, to ensure that optical signals can be emitted with just-enough power to ensure targeted BER. As a result, most promising solutions are highlighted for mapping a defined application onto a 16-core ring-based WDM ONoC.

Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping

To face the complex communication problems that arise as the number of on-chip components grows up, photonic networks-on-chip (NoCs) have been recently proposed to replace electronic interconnects. However, photonic NoCs lack efficient laser sources, possibly resulting in an inefficient or inoperable architecture. In this article, we introduce a methodology for the design space exploration of optical NoC mapping solutions, which automatically assigns IPs/cores to the network tiles such that the laser power consumption is minimized. The experimental evaluation shows average reductions of 34.7% and 27.3% in the power consumption compared to, respectively, application-oblivious and randomly mapped photonic NoCs, allowing improved energy efficiency.

Scheduling in Multi-Wavelength Ring-Based Optical Networks-on-Chip

Synchronous networks-on-chip (NoC) require tailored schedulers achieving low latency, high throughput, and fairness while avoiding packet collisions. Efficient schedulers exist for rearrangeable non-blocking NoC. However, NoCs fabricated in integrated photonics typically suffer a blocking behavior due to the limitations of the switching capabilities in the space and wavelength domains. This paper discusses a scheduler for an integrated optical NoC based on a ring topology and realized with multiple resonating microrings (multi-microring, MMR). Scheduling in MMR architecture consists of the conventional matching sub-problem and the wavelength assignment sub-problem. The paper’s contribution is twofold. An iterative parallel wavelength matching (iPWM) algorithm is presented for jointly addressing both sub-problems. iPWM achieves performance similar to a two-step scheduler based on sequential iSLIP and first-fit wavelength assignment, but with a computational complexity lower than and independent of the number of wavelengths. A comprehensive comparison with the two-step scheduler based on the more complex maximum weighted matching algorithm and with an optimal scheduler is also carried out for the case of fixed and tunable transmitters to assess the trade-off between scheduling complexity and performance. In addition, bidirectionality with one or two transceivers per port is proposed as a way to overcome the throughput degradation caused by the blocking behavior. Simulation results indicate that bidirectionality is very effective in improving the throughput and reducing the latency even when using a single transceiver.

A Thermal-Aware Power Allocation Method for Optical Network-on-Chip

Optical network on chip (ONoC) is a promising on-chip communication architecture for future many-core systems due to its high performance and energy efficient. ONoC is mostly constructed with microring resonators. However, thermo-optic effect will lead to the drift of the operation point and ultimately have a serious impact on the signal-to-noise rate (SNR). In order to solve this problem, a thermal-aware power allocation method is proposed in this paper. Every communication request should be provided with enough power to satisfy the minimum SNR requirement. Time division multiplexing technology is adopted to solve the power allocation conflicts and communication path conflicts in the network. In order to minimize the number of slots satisfying the rated power supply, an optimization model is established and solved. The simulation results indicate that our proposed method can increase the success rate of communication requests from an average of 43% to 100% in four different on-chip thermal distribution scenarios when compared with four communication scenarios without optimization. It also saves 66.7% of the laser power in average compared with the traditional power allocation method.

Venus: A Low-Latency, Low-Loss 3-D Hybrid Network-on-Chip for Kilocore Systems

Network on chip (NoC) with more than 1000 cores is anticipated to meet the requirements of exascale computing in the foreseeable future. As latency is one of the most critical metrics to evaluate performance for kilocore-chip, researchers recently proposed optical networks on chip (ONoCs) with multiwavelength to achieve low latency. Nevertheless, with networks scaling to kilocores and too many wavelengths used, waveguide crossings loss and microring resonators (MRs) pass-by loss on the critical path are increased considerably. In this paper, we propose Venus, a three-dimensional NoC architecture with multiple photonic and electrical layers. By using space division multiplexing and hybrid wavelength assignments method, Venus possesses the following two features: 1) Each core can communicate with any other one in one hop and any two clusters in different subnets can communicate with each other without any blocking, thus reducing latency greatly; and 2) the number of waveguide crossings and also the MRs passed by on the critical path is reduced, thus saving energy consumption considerably. Architectures based on 64-core, 512-core, and 1024-core are simulated respectively. Evaluation results of different synthetic traffic patterns and real applications demonstrate that Venus significantly reduces the end-to-end latency and worst case loss compared to previous proposals.

A Survey on Optical Network-on-Chip Architectures

Optical on-chip data transmission enabled by silicon photonics (SiP) is widely considered a key technology to overcome the bandwidth and energy limitations of electrical interconnects. The possibility of integrating optical links into the on-chip communication fabric has opened up a fascinating new research field—Optical Networks-on-Chip (ONoCs)—which has been gaining large interest by the community. SiP devices and materials, however, are still evolving, and dealing with optical data transmission on chip makes designers and researchers face a whole new set of obstacles and challenges. Designing efficient ONoCs is a challenging task and requires a detailed knowledge from on-chip traffic demands and patterns down to the physical layout and implications of integrating both electronic and photonic devices. In this paper, we provide an exhaustive review of recently proposed ONoC architectures, discuss their strengths and weaknesses, and outline active research areas. Moreover, we discuss recent research efforts in key enabling technologies, such as on-chip and adaptive laser sources, automatic synthesis tools, and ring heating techniques, which are essential to enable a widespread commercial adoption of ONoCs in the future.

A novel IP-core mapping algorithm in reliable 3D optical network-on-chips

The Optical Network-on-Chip (ONoC) is considered as a promising way to achieve high performance of multiprocessor systems, and it will be a 3-Dimensional (3D) architecture organized by a certain topology where optical routers are optically interconnected with each other. For the design of 3D ONoCs, the highly reliable IP-core mapping is a key problem of properly assigning IP cores onto optical routers for a given communication task, and it has two main challenges: reliability estimation and mapping scheme. As for reliability estimation, crosstalk noise and thermal sensitivity which severely influence Signal-Noise-Ratio (SNR) should be measured. In addition, although standard genetic algorithms have been widely utilized to solve the optimal mapping solution due to the superiority of simple process, there are some deficiencies such as premature convergence and inferior local searching. In this paper, the impact factors of ONoC reliability are measured by SNR and thermal models, and we also design a novel IP-core mapping algorithm called as CGSA (Cataclysm Genetic-based Simulated Annealing) based on proposed models. In CGSA, we integrate genetic with an improved simulated annealing algorithm assorted with cataclysm strategies, in order to speed up the searching process. Furthermore, to enhance the network reliability, CGSA is bound with the topology selection, i.e., CGSA generates the optimal mapping solution with the best matched 3D ONoC topology. Simulation results show that CGSA is effective on achieving the higher reliability than benchmarks.

A blocking optimization method by convergence of cores for application-based optical circuit switched network-on-chip

With the development of technology of integrated circuit (IC), there will be several hundred million or even several billion transistors in one chip. Optical network on chip (ONoC) has been identified as an effective communication architecture to achieve better performance in delay and energy consumption. However, in circuit switched ONoC, the blocking situation degrades the performance severely. In this paper, a method that converge intellectual property (IP) cores with the same destination address or the same source address is proposed to reduce the blocking probability in circuit switched ONoC. We compare the proposed converged circuit switched ONoC with non-converged circuit switched ONoC in terms of end-to-end (ETE) delay and energy dissipation under various applications. The simulation results show that the converged ONoC improves the ETE delay with small change in energy efficiency.

Exploring crosstalk noise generated in the N-port router used in the WDM-based ONoC

Compared with optical network-on-chip (ONoC) with single wavelength, ONoC adopting wavelength division multiplexing (WDM) technology possesses a very prominent advantage—higher bandwidth. Therefore, WDM-based ONoC has been considered one of the most promising ways to relieve the rapidly increasing traffic load in communication systems. A WDM-based router, as the core equipment of WDM-based ONoC, is influenced by crosstalk noise, especially the nonlinear crosstalk noise generated by the four-wave mixing effect. Thus, to explore the performance of the N-port nonblocking optical router using WDM, we propose a universal analytic model to analyze the transmission loss, crosstalk noise, optical signal-to-noise ratio (OSNR), and bit error ratio (BER). The research results show that crosstalk noise varies along with signals at different wavelengths in the same channel. For signals with the same wavelength, the noises generated in the different transmission paths are obviously different from each other. For research of transmission loss, OSNR, and BER, similar results can be obtained. Based on the eye diagrams, we can learn that crosstalk noise will cause signal distortion to a certain extent. With this model, capability of this kind of multiport optical router using WDM can be understood conveniently.

Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System

A realistic assessment of optical networks-on-chip (ONoCs) can be performed only in the context of a comprehensive floorplanning strategy for the system as a whole, especially when the 3-D stacking of electronic and optical layers is implemented. This paper fosters layout-aware ONoC design by developing a physical mapping methodology for wavelength-routed ONoC topologies subject to the floorplanning, placement, and routing constraints that arise in a 3-D-stacked environment. As a result, this paper is able to compare the power efficiency and signal-to-noise ratio of ring-based versus filter-based wavelength-routed topologies as determined by their physical design flexibility.