Transceiver For Optical Interconnects Research Articles

Comprehensive vertical-cavity surface-emitting laser model for optical interconnect transceiver circuit design

Directly modulated vertical-cavity surface-emitting lasers (VCSELs) are commonly used in short-reach optical interconnect applications. To enable efficient optical interconnect transceiver systems operating at data rates up to 25 Gb/s and beyond, cosimulation environments, which allow for the optimization of driver circuitry with accurate compact VCSEL models, are necessary. A comprehensive VCSEL model, which captures thermally dependent electrical and optical dynamics and provides direct current, small-, and large-signal simulation capabilities with self-consistency, is presented. The device’s electrical behavior is described with an equivalent circuit, which captures both large-signal operation and electrical parasitics, while the optical response is captured with a rate-equation-based model. Bias and temperature dependencies are incorporated into both key electrical and optical model parameters. Experimental verification of the model is performed at 25 Gb/s with a 990-nm VCSEL to study the impact of bias current level and substrate temperature.

A Compact Verilog-A Model of Silicon Carrier-Injection Ring Modulators for Optical Interconnect Transceiver Circuit Design

Optical interconnect system efficiency is dependent on the ability to optimize the transceiver circuitry for low-power and high-bandwidth operation, motivating co-simulation environments with compact optical device simulation models. This paper presents a compact Verilog-A silicon carrier-injection ring modulator model, which accurately captures both non-linear electrical and optical dynamics. The device's electrical behavior is described by a p-i-n diode SPICE model, while the optical response is captured with a dynamic ring resonator model, which considers the ring's cumulative phase shift. Experimental verification of the model is performed both at 8 Gb/s with symmetric drive signals to study the impact of pre-emphasis pulse duration, pulse depth, and dc bias, and at 9 Gb/s with a 65 nm CMOS driver capable of asymmetric pre-emphasis pulse duration. The potential for 15 Gb/s operation is shown by utilizing the presented model for optimization of the asymmetric pre-emphasis signal waveform.

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm2.

An Optical Interconnect Transceiver at 1550 nm Using Low-Voltage Electroabsorption Modulators Directly Integrated to CMOS

A low-voltage, 90-nm CMOS optical interconnect transceiver operating at 1550-nm optical wavelength is presented. This is the first demonstration of a novel optoelectronic modulator architecture (the quasi-waveguide angled-facet electroabsorption modulator) in a system. It features a simple electronic packaging via flip-chip bonding to silicon. Devices have a broad optical bandwidth, are arrayed two dimensionally, and feature surface normal, spatially separated, and misalignment-tolerant optical ports. The modulators are driven with a novel pulsed-cascode driver capable of supplying an output-voltage swing of 2 V (twice the nominal 1-V CMOS supply) without overstressing thin-oxide core CMOS devices. At the receiver side, a sensitivity of -15.2 dBm is obtained with an integrating/double-sampling front end. The transceiver includes clock generation and recovery circuitry that enables a data serialization factor of five. At a maximum data rate of 1.8 Gb/s, the optical transmitter, receiver, and clocking circuitry consume 12.6, 4.5, and 6.5 mW, respectively, for a total link electrical power dissipation of 23.6 mW. To the best of our knowledge, this is the first demonstration of an interconnect transceiver operating at 1550 nm with a III-V output device directly integrated to the CMOS.