Performance Power Consumption Research Articles

A microgripper based on electrothermal Al–SiO2 bimorphs

Microgrippers are essential for assembly and manipulation at the micro- and nano-scales, facilitating important applications in microelectronics, MEMS, and biomedical engineering. To guarantee the safe handling of delicate materials and micro-objects, a microgripper needs to be designed to operate with exceptional precision, rapid response, user-friendly operation, strong reliability, and low power consumption. In this study, we develop an electrothermal actuated microgripper with Al-SiO2 bimorphs as the primary structural element. The fabricated microgripper naturally adopts a closed state due to process-induced residual stresses. The thermal expansion mismatch between Al and SiO2 allows for an easy transition of the microgripper between open and closed states by temperature control. Experimental data reveal that the microgripper can achieve impressive deformability, bending over 100 degrees at just 5 V, and responding within 10 ms. Its capability to handle micro-objects is verified using polymethyl methacrylate (PMMA) microbeads and its gripping strength is quantitatively assessed. It is demonstrated that the microgripper holding a microbead with a diameter of 400 μm and a weight of 0.1 mg can withstand an average acceleration of 35 g during vibration test and over 1600 g in impact tests, highlighting its exceptional grasping performance. Additionally, the “pick-and-place” task for handling and positioning solder beads (0.25 mg for each bead) with diameters of 400 μm on a bulk silicon inductor chip has been successfully completed. This unique microgripper is anticipated to be highly beneficial for various micro-assembly and micromanipulation applications, particularly in the field of electronic packaging.

A Miniaturized and Ultra-Low-Power Wireless Multi-Parameter Monitoring System with Self-Powered Ability for Aircraft Smart Skin

The aircraft smart skin (ASS) with structural health monitoring capabilities is a promising technology. It enables the real-time acquisition of the aircraft’s structural health status and service environment, thereby improving the performance of the aircraft and ensuring the safety of its operation, which in turn reduces maintenance costs. In this paper, a miniaturized and ultra-low-power wireless multi-parameter monitoring system (WMPMS) for ASS is developed, which is capable of monitoring multiple parameters of an aircraft, including random impact events, vibration, temperature, humidity, and air pressure. The system adopts an all-digital monitoring method and a low-power operating mechanism, and it is integrated into a low-power hardware design. In addition, considering the airborne resources limitations, an energy self-supply module based on a thermoelectric generator (TEG) is developed to continuously power the system during flight. Based on the above design, the system has a size of only 45 mm × 50 mm × 30 mm and an average power consumption of just 7.59 mW. Through experimental validation, the system has excellent performance in multi-parameter monitoring and operating power consumption, and it can realize the self-supply of energy.

Low Power Gas Sensors: From Structure to Application.

Gas sensors are pivotal across industries, encompassing environmental monitoring, industrial safety, and healthcare. Recently, a surge in demand for low power gas sensors has emerged, driven by the huge need for applications in portable devices, wireless sensor networks, and the Internet of things (IoT). The practical realization of a densely interconnected sensor network demands gas sensors to have low power consumption for energy-efficient operation. This Perspective offers a comprehensive overview of the progress of low-power sensors for gas and volatile organic compound detection, with a keen focus on the interplay between sensing materials (including metal oxide semiconductors, metal-organic frameworks, and two-dimensional materials), sensor structures, and power consumption. The main gas sensing mechanisms are discussed, and we delve into the mechanisms for achieving low power consumption including material properties and sensor design. Furthermore, typical applications of low power gas sensors are also presented, including wearable technology, food safety, and environmental monitoring. The review will end by discussing some open questions and ongoing needs.

Thermal management system for prismatic lithium-ion batteries coupling with U-type channels and pyrolytic graphite honeycomb fins

The battery thermal management system (BTMS) is crucial for the safety and lifespan of electric vehicles. This paper proposes a hybrid BTMS combining liquid cooling plates arranged on the side and pyrolytic graphite honeycomb fins (PGHF). The cold plate contains two U-type channels with staggered inlets, and the phase change material (PCM) is filled in the honeycomb fins. The internal resistance and entropic coefficient of the battery are obtained experimentally and used to model the battery’s heat production. The heat dissipation capabilities of six different BTMS are compared at a discharge rate of 3C. Compared with traditional serpentine cold plate cooling, the designed BTMS reduces the maximum temperature, maximum temperature difference, and pressure drop by 5.32 K, 6.82 K, and 462.94 Pa, respectively, indicating significant improvements in cooling performance and substantial reductions in system power consumption. In this paper, the effects of different inlet mass flow rates and honeycomb fin porosity on the heat dissipation of the system are investigated to determine their optimal values. Results indicate that when the mass flow rate is 1.0 g∙s−1 and the honeycomb fin porosity is 45.68 %, the maximum temperature of the battery is 310.38 K, the maximum temperature difference is 1.82 K, and the pressure drop is 279.35 Pa, which represents the optimal cooling performance.

Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology

ABSTRACTThe error tolerance nature of the digital multimedia applications enables the implementation of approximate digital circuits to achieve the benefits of high speed of operation and low power consumption. This paper proposes a static approximate modified mirror full adder (SAMM‐FA) circuit designed using logic level approximation to reduce the number of transistors in the circuit. Owing to the balanced electrical characteristics, better stability and higher on‐current to off‐current ratio (Ion/Ioff), 32 nm carbon nanotube field effect transistor (CNTFET) technology has been used for implementing the proposed circuit in the Cadence Virtuoso tool. Featuring only 10 transistors and operating at a supply voltage of 0.5 V, the proposed SAMM‐FA has a low power dissipation of just 4.14 nW, and propagation delay of just 3.82 ps. The power delay product and energy delay product figure of merits of the proposed circuit are found to be excellent when compared with the contemporary designs.

Revealing Fast Negative Capacitance in PbZr0.2Ti0.8O3 Thin Film with Acicular Ferroelastic Domains.

Negative capacitance effects with fast response times hold great potential for reducing the power consumption in high-frequency nanoelectronics. Nevertheless, the negative capacitance effect faces considerable complexity arising from the dynamic interplay among electrostatic, nucleation energies, and domain evolution. This intricate balance poses a formidable challenge to achieving fast negative capacitance. Herein, we have achieved a fast negative capacitance time of ∼16.23 ns in PbZr0.2Ti0.8O3 (PZT) thin film, and our investigation confirms the presence of acicular ferroelastic domains within the PZT thin film. Under reversal electric fields, these acicular ferroelastic domains undergo a unique flipping process, transitioning through domain expansion and contraction. This distinct domain flipping manner accelerates the nucleation and growth of ferroelectric domains, thereby facilitating the observed fast negative capacitance. The realization of fast negative capacitance holds substantial promise for reducing operational time and power consumption, offering prospects for the design of nanoelectronics with significantly lower power requirements.

Dual-band all-optical logic gate based on coherent control principles

In this paper, we present a dual-band all-optical logic gate based on a coherent perfect absorption metasurface. By utilizing the principle of coherent perfect absorption, we can manipulate the interference between two input signals by adjusting their relative phase difference. This allows us to implement logic functions such as AND, OR, and XOR in the second (1310 nm) and third (1550 nm) windows of the communication band. Moreover, we present the concept of "contrast" as a quantitative metric to assess the performance of each logic gate. The simulation results show that the contrast between the AND gate and the XOR gate can reach 6.4 dB and 17.8 dB at 1310 nm, as well as 6.1 dB and 18.9 dB at 1550 nm, rendering it highly advantageous for practical applications. The realization of ultrafast operation and low power consumption in coherent perfect absorption metasurfaces would significantly contribute to advancing the progress of optical data processing.

Dynamic Clock Switching Scheme for Enhanced Power Efficiency in System-on-Chip Architectures

High power consumption and thermal management are critical challenges in traditional System- on-Chip (SoC) architectures due to multiple active clock sources feeding individual IP blocks, even during idle states. This paper introduces a dynamic clock switching power-saving scheme that consolidates clock sources by dynamically switching to a single lower-frequency clock during low-power modes. A Clock Control Agent (CCA) monitors real-time operational status, power consumption, and performance needs, leveraging AI for predictive adjustments. Experimental results demonstrate a significant reduction in idle power consumption and improved thermal management, without compromising performance or data integrity. This scheme addresses inefficiencies in existing methods such as Dynamic Voltage and Frequency Scaling (DVFS) and clock gating, offering a robust and efficient solution for next-generation SoC designs.

Growth and characterization of micro-LED based on GaN substrate.

As the diminution of micro-LED pixels advances, the pivotal role of dislocation phenomena becomes increasingly pronounced. This study provides insight into the key characteristics and dominant mechanisms of GaN-based micro-LEDs by comparing the homoepitaxial and heteroepitaxial configurations. Our findings reveal that variability in V-shaped pits distribution markedly influences the performance and uniformity of micro-LED chips. While the homoepitaxial micro-LEDs, alongside significantly reduced dislocation density and residual stress, effectively preclude the formation of them and thus ensuring superior uniformity both within and among micro-LED chips. Notably, the external quantum efficiency (EQE) peak of homoepitaxial micro-LEDs surpasses that of heteroepitaxial variants by 40%. Motivated by the realization that the reduced MQW thickness at the sidewalls of V-shaped pit aids carrier injection, a great enhancement in EQE from 7.9% to 14.8% (@ 10 A/cm2) was achieved by the optimization of homoepitaxial structure. Therefore, the growth of micro-LED with lower dislocation density, lower residual stress, and epi-structure of low-energy-barrier MQWs demonstrated the profound impact on advancing micro-LED technology to obtain the performance of high uniformity, high brightness, and low power consumption.

Vertical Cavity Surface Emitting Laser technology: A comprehensive review

Vertical Cavity Surface Emitting Laser (VCSEL) technology has become an indispensable element in optical communication systems and optoelectronics due to its many advantages, and the unique characteristics of VCSELs, including vertical emission, high-speed operation, and low power consumption, have attracted much interest from researchers and industry professionals. This paper provides a comprehensive overview of VCSELs, explaining their basic principles and two commonly used structures. It also delves into the field of optical communications, highlighting the challenges faced in the current development, from which it introduces the significant progress made by VCSELs over the past decade in various applications such as high-speed data transmission, multi-mode communications, and long-distance networks. In addition, this study provides valuable insights into the future trajectory and potential evolution of VCSEL technology to facilitate further research and innovation in the field of communications. By providing a holistic analysis, this study is a valuable resource for scientists and researchers to help them realize the full potential of VCSELs in advancing optical communication technologies to meet the ever-changing needs of modern communication networks.

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Ferroelectric transistors based on hafnia-based ferroelectrics exhibit tremendous potential as next-generation memories owing to their high-speed operation and low power consumption. Nevertheless, these transistors face limitations in terms of memory window, which directly affects their ability to support multilevel characteristics in memory devices. Furthermore, the absence of an efficient operational technique capable of achieving multilevel characteristics has hindered their development. To address these challenges, we present a gate stack engineering method and an efficient operational approach for ferroelectric transistors to achieve 16-level data per cell operation. By using the suggested engineering method, we demonstrate the attainment of a substantial memory window of 10 V without increasing the device area. Additionally, we propose a displacement current control method, facilitating one-shot programming to the desired state. Remarkably, we suggest the compatibility of these proposed methods with three-dimensional (3D) structures. This study underscores the potential of ferroelectric transistors for next-generation 3D memory applications.

Optimized Design and Operation Control of Refrigerant Direct Cooling Thermal Management System for Power Battery

In order to solve the compatibility problem of lithium batteries thermal management and cabin comfort in electric vehicles, a refrigerant direct cooling thermal management system is designed in this article, which is expected to balance the temperature demands of entire vehicle at different driving conditions. A one‐dimensional model is established to investigate the system performance, whose accuracy has been verified by the testing bench of a prototype fixed with a 16‐battery module. By the aid of this model, the thermal characteristics of the battery pack and the passenger cabin are obtained, and the compressor speed as well as the valves are selected as control units by sensitivity analysis of the important components. Subsequently, detailed control strategies around the variable frequency of compress speed and switch regulation for the valves are proposed based on the temperature changes, torque, and operating power consumption of the system in different control modes. Under the test conditions of the global light‐duty vehicle test procedure, it is found that cabin temperature can be quickly stabilized about 26 °C under different ambient temperatures. Additionally, the battery pack can be effectively maintained within the safe operating temperature range of 20–40 °C.

Optimization of waveguide fabrication processes in lithium-niobate-on-insulator platform.

Lithium niobate (LN) is used in diverse applications such as spectroscopy, remote sensing, and quantum communications. The emergence of lithium-niobate-on-insulator (LNOI) technology and its commercial accessibility represent significant milestones. This technology aids in harnessing the full potential of LN's properties, such as achieving tight mode confinement and strong overlap with applied electric fields, which has enabled LNOI-based electro-optic modulators to have ultra-broad bandwidths with low-voltage operation and low power consumption. Consequently, LNOI devices are emerging as competitive contenders in the integrated photonics landscape. However, the nanofabrication, particularly LN etching, presents a notable challenge. LN is hard, dense, and chemically inert. It has anisotropic etch behavior and a propensity to produce material redeposition during the reactive-ion plasma etch process. These factors make fabricating low-loss LNOI waveguides (WGs) challenging. Recognizing the pivotal role of addressing these fabrication challenges for obtaining low-loss WGs, our research focuses on a systematic study of various process steps in fabricating LNOI WGs and other photonic structures. In particular, our study involves (i) careful selection of hard mask materials, (ii) optimization of inductively coupled plasma etch parameters, and finally, (iii) determining the optimal post-etch cleaning approach to remove redeposited material on the sidewalls of the etched photonic structures. Using the recipe established, we realized optical WGs with total (propagation and coupling) loss value of -10.5 dB, comparable to established values found in the literature. Our findings broaden our understanding of optimizing fabrication processes for low-loss lithium-niobate waveguides and can serve as an accessible resource in advancing LNOI technology.

基于ANSYS/LS-Dyna旋耕刀切土仿真分析及优化

Mini-tiller is an indispensable agricultural machinery in hilly and mountainous areas of China. Rotary blade is an important working part of mini-tiller, which directly affects the operation quality and power consumption of mini-tiller. In order to reduce the cutting resistance and power consumption of the rotary blade of mini-tiller, the cutting process of the rotary blade was analyzed by numerical simulation, and the tangential bending radius (R), bending angle (β) and edge thickness (c) of the rotary blade were selected as factors to optimize it. After comparing the cutting resistance and cutting power consumption of the rotary blade before and after optimization, the results show that the cutting force of the optimized rotary blade is smaller than that of the rotary blade before optimization. The cutting power consumption of the optimized rotary blade is 2.4% lower than that of the unoptimized rotary blade, which achieves the purpose of drag reduction and consumption reduction.

4 Gbps serializer circuits in a 180 nm technology for monolithic pixel sensor prototypes developed for the CEPC vertex detector

Monolithic Active Pixel Sensor is one of the promising candidates for the Circular Electron Positron Collider Vertex detector, due to its good performance and trade-off of granularity, readout speed, material budgets and power consumption. A full-scale TaichuPix chip, including a matrix of 512 × 1024 pixels with a size of 25 × 25 μm2 is developed to provide a spatial resolution better than 5 μm. It requires a raw data rate up to 3.84 Gbps and power consumption less than 100 mA for the serializer circuit. Based on one of the small-scale prototypes, the highest serial data rate is tested to be 3.36 Gbps with a peak-to-peak jitter of about 150 ps and large current consumption. Moreover, the 32-bit parallel data width of the serializer isn't suitable for the 8B10B encoder. Therefore, two 4 Gbps serializers have been designed and optimized to meet these requirements based on the same process node of 180 nm as the TaichuPix, considering the funding and time costs. The serializer consists of a phase locked loop (PLL), several 5:1 sub-multiplexers based on a shift-register chain, a 4:1 or 8:1 sub-multiplexer based on the binary-tree structure, a clock distributor and a high-speed driver. Both ring-oscillating PLL and LC-tank PLL were integrated for performance evaluation. The preliminary tests showed low-jitter characteristics of the two PLLs despite this version's biasing problem, and both serializer circuits functioned correctly. A revision corrected the error and was submitted in October 2023.

Hardware-Accelerated YOLOv5 Based on MPSoC

This paper details the development of a hardware acceleration system for YOLOv5, focusing on flame detection as its primary application. The implementation leverages the APU and DPU functionalities integrated into the Zynq UltraScale+ MPSoC XCZU7EV core. The proposed solution addresses the challenge of achieving real-time target detection on mobile terminals, ensuring both real-time operation and ultralow power consumption of YOLOv5. Notably, our design approach facilitates the deployment of all target detection algorithms under TensorFlow for mobile devices. To optimize model efficiency, we employ saturated linear mapping quantization with calibration. This technique maps model weights, double bases, and activations from 32-bit to 8-bit, incurring only a 1.64% accuracy loss. The data flow design is realized through efficient data exchange between DDR, APU, and DPU, utilizing the AXI4 bus architecture. Image pre-processing and post-processing tasks are executed on the APU, while neural network inference occurs on the DPU. Our accelerated system demonstrates compelling experimental results: maintaining a detection speed of 56FPS, achieving an accuracy of 36.56% on the COCO2014 dataset, and exhibiting a total system power consumption of only 4.147W. Furthermore, the energy consumption ratio is measured at 15.41GOPS/W, surpassing the RTX A6000 graphics card by a factor of 55.

Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA

Electrocardiogram (ECG) signals are commonly used to diagnose heart-related diseases. However, noise induced during the measurement process can affect the accuracy of the diagnosis. Digital filters, such as the Finite Impulse Response (FIR) filter, are widely used to filter out noise from the ECG signal. Nevertheless, the processing speed of software-based FIR filters is slow for large ECG datasets due to serial processing. This paper presents a hardware implementation of the FIR filter for ECG signal processing to overcome the processing speed issue. The filter is designed using the Kaiser Window method and implemented on the Intel Cyclone IV Field Programmable Gate Array (FPGA). The filter is first designed in MATLAB to obtain the filter coefficients where the ECG data were obtained from Physionet database. From the difference equation, we designed the signal flow graph (SDFG) and then mapped into hardware logics to enable parallel processing. Simulation results of the software (MATLAB) and hardware (FPGA) implementations are obtained and compared. The results show that the FPGA-based FIR filter can process the ECG signal up to 1,250 times faster than software implementations. To further optimize the design and reduce hardware cost, we introduce optimized designs by applying the operation scheduling and constrained resource allocation techniques. The maximum operating frequency, logic utilization, and power consumption of each design were analysed and compared. This study demonstrates that custom-designed hardware logic for digital signal processing can significantly outperform software implementations due to its parallel processing capabilities. The proposed optimization techniques reduce the hardware cost while maintaining high processing speed and accuracy. The hardware implementation of the FIR filter for ECG signal processing has numerous applications in diagnosing heart-related diseases and real-time monitoring of ECG signals in critical care settings.

General-purpose programmable photonic processor for advanced radiofrequency applications

A general-purpose photonic processor can be built integrating a silicon photonic programmable core in a technology stack comprising an electronic monitoring and controlling layer and a software layer for resource control and programming. This processor can leverage the unique properties of photonics in terms of ultra-high bandwidth, high-speed operation, and low power consumption while operating in a complementary and synergistic way with electronic processors. These features are key in applications such as next-generation 5/6 G wireless systems where reconfigurable filtering, frequency conversion, arbitrary waveform generation, and beamforming are currently provided by microwave photonic subsystems that cannot be scaled down. Here we report the first general-purpose programmable processor with the remarkable capability to implement all the required basic functionalities of a microwave photonic system by suitable programming of its resources. The processor is fabricated in silicon photonics and incorporates the full photonic/electronic and software stack.

Challenges of Using Fuel Cells to Deliver Aircraft Propulsion Power

Beside sustainable aviation fuels (SAFs), which offer an easy but expensive drop-in solution the use of hydrogen is discussed as an important way to decarbonise air traffic. According to a study performed by McKenzie on behalf of the “Fuel Cell and Hydrogen 2” and “Clean Sky 2” Joint undertakings hydrogen is the economical more viable option for small and medium range aircrafts1. For the smaller aircrafts electric propulsion using fuel cells to deliver the required electric power are the preferred choice from the economic perspective.Operating fuels cell on board of a flying aircraft is however not necessarily easy. An evident issue is the reduced air pressure at high altitudes. So, the barometric pressure at an altitude of 11,000 m is only 0.29 bar. Oxygen partial pressure is equally reduced to 61 mbar at constant oxygen concentration of 21 vol.%. In order to supply the stack either much higher flow rates are required at reduced pressures or a much higher compression. The former will create challenges regarding water management as a high gas flow in combination with reduced pressure accelerates the drying out of the membrane. Using HT-PEMFC instead would avoid the impact of water evaporation. However, the conditions are also likely to foster evaporation of phosphoric acid from the membrane electrode assembly. Here it will be investigate from published data if new HT-PEMFC membranes e.g. from Los Alamos National Laboratory2 would allow such a low pressure operation. Operating at high pressure will definitively challenge the system efficiency. Also, the characteristics of typical compressors render it difficult to achieve the required air compression rate of about 4.5 to increase pressure from 0.29 bar ambient to 1.3 bar stack pressure. This is, because during typical cruise operation power consumption and thus air need is strongly reduced.The variation of load and subsequently the likely variation of stack pressure can also cause challenges, in particular if after a period of low power requirements, a sudden increase in power demand needs to be answered. Such a situation will regularly be encountered for high load take off acceleration after taxying and potential waiting. Here hybridisation with a battery can be helpful to allow the fuel cell to power-up in time before take-off charging the battery used for electric taxying. More difficult is the irregular but for safety reason important situation of a go-around. During descend engines are typically operated at close to idle condition for a longer period of time. If no measures are taken to maintain stack temperature the temperature will reduce so that the immediate supply of power required for a go-around might not be available. Keeping the temperature at low load may however again cause dry-out or acid evaporation depending on whether the stack is LT- or HT-PEMFC based.In this contribution are more detailed analysis will be presented also striving to assign issues and their potential mitigation to component, stack or system level. Hydrogen-powered aviation: A fact-based study of hydrogen technology, economics, and climate impact by 205 0, Luxembourg, Publications Office of the European Union.K.-S. Lee, S. Maurya, Y. S. Kim, C. R. Kreller, M. S. Wilson, D. Larsen, S. E. Elangovan and R. Mukundan, Energy Environ. Sci., 11(4), 979–987 (2018).

Design and Optimization of Reversible Arithmetic Unit Using Modified Gate Diffusion Input Logic

ABSTRACTIncreasing integration levels and demand for portability have made minimising the power consumption of circuits increasingly important for wide range of applications. Reversible logic is a low-power, low-loss design that can be utilised in low power CMOS, optical computing, nanotechnology, and quantum computing. Quantum machine learning Research is an area examines combining ideas from quantum computing and machine learning. In this paper, a new design of reversible logic-based arithmetic unit is demonstrated with CMOS and modified-GDI (MGDI) methodology for nanoscales using reversible gates. We provide a design for an optimized arithmetic unit, as well as some proposed methodologies for designing a reversible arithmetic unit with novel reversible gates, and compare them to existing circuits in terms of garbage output, constant input, number of reversible gates, and quantum cost, in this work. It can also be employed in Quantum computers due to its lower Quantum Cost and Garbage Output. Transistor-level implementations of the proposed arithmetic units are accomplished using Cadence Virtuoso tool GPDK 90 nm technology in combination with CMOS and MGDI techniques. Due to the optimization, the proposed arithmetic unit shows better performance in worst-case delay and power consumption than a comparable non-optimized Arithmetic Unit. According to the design and analysis of proposed Arithmetic Units. The proposed −1 design of the 4-bit Arithmetic Unit achieves optimisation by incorporating a reduced number of reversible gates and exhibiting a low quantum cost (12&40) using MGDI-FS. Similarly, the proposed −2 and 3 designs minimizes the number of transistors required, with a count of 80 and 120, and proposed −3 design, it eliminates the presence of constant inputs entirely using MGDI-FS.