Operand Pairs Research Articles

Faster multiplication over $${\mathbb {F}}_2[X]$$ using AVX512 instruction set and VPCLMULQDQ instruction

Code-based cryptography is one of the main propositions for the post-quantum cryptographic context, and several protocols of this kind have been submitted on the NIST platform. Among them, BIKE and HQC are part of the five alternate candidates selected in the third round of the NIST standardization process in the KEM category. These two schemes make use of multiplication of large polynomials over binary rings, and due to the polynomial size (from 10,000 to 60,000 bits), this operation is one of the costliest during key generation, encapsulation, or decapsulation mechanisms. In BIKE-2, there is also a polynomial inversion which is time-consuming and this problem has been addressed in Drucker (Fast polynomial inversion for post quantum QC-MDPC cryptography, 2020). In this work, we revisit the different existing constant-time algorithms for arbitrary polynomial multiplication. We explore the different Karatsuba and Toom–Cook constructions in order to determine the best combinations for each polynomial degree range, in the context of AVX2 and AVX512 instruction sets. This leads to different kernels and constructions in each case. In particular, in the context of AVX512, we use the VPCLMULQDQ instruction, which is a vectorized binary polynomial multiplication instruction. This instruction deals with up to four polynomial (of degree up to 63) multiplications, that is four operand pairs of 64-bit words with 128-bit word storing each result, the four results being stored in one single 512-bit word. This allows to divide by roughly 3 the retired instruction number of the operation in comparison with the AVX2 instruction set implementations, while the speedup is up to 39% in terms of processor clock cycles. These results are different than the ones estimated in Drucker (Fast multiplication of binary polynomials with the forthcoming vectorized vpclmulqdq instruction, 2018). To illustrate the benefit of the new VPCLMULQDQ instruction, we used the HQC code to evaluate our approaches. When implemented in the HQC protocol, for the security levels 128, 192, and 256, our approaches provide up to 12% speedup, for key pair generation.

Simulation of the Super-scalar Processor Core Operation

The article considers the features of super-scalar processors, their way of performing several operations on several pairs of operands simultaneously. The research focuses on the organization of processor pipeline execution operation of several machine instructions in one processor core. The simulating kit was developed for better understanding of a processor core microarchitecture. It includes two parts: program and methodical recommendations with multiple task options. The simulating kit demonstrates the pipeline architecture consisting of two clusters: front-end and back-end and the principle of translating complex multi-cycle CISC-like instructions into simpler RISC-like micro-operations. The main types of machine instructions are considered: data transfer between registers and memory cells (four variations), data processing of couple of operands from registers and memory cells (four variations), conditional jump to the specified address. The program-simulator makes it possible to conduct a more detailed simulation of one of the three mechanisms for calculations accelerating in the processor core: multi-functional (super-scalar) processing, out-of-order processing, speculative instructions execution after the branch prediction. The simulating kit is used in educational process when training masters of Higher School of Economics National Research University.

Children learn spurious associations in their math textbooks: Examples from fraction arithmetic.

Fraction arithmetic is among the most important and difficult topics children encounter in elementary and middle school mathematics. Braithwaite, Pyke, and Siegler (2017) hypothesized that difficulties learning fraction arithmetic often reflect reliance on associative knowledge-rather than understanding of mathematical concepts and procedures-to guide choices of solution strategies. They further proposed that this associative knowledge reflects distributional characteristics of the fraction arithmetic problems children encounter. To test these hypotheses, we examined textbooks and middle school children in the United States (Experiments 1 and 2) and China (Experiment 3). We asked the children to predict which arithmetic operation would accompany a specified pair of operands, to generate operands to accompany a specified arithmetic operation, and to match operands and operations. In both countries, children's responses indicated that they associated operand pairs having equal denominators with addition and subtraction, and operand pairs having a whole number and a fraction with multiplication and division. The children's associations paralleled the textbook input in both countries, which was consistent with the hypothesis that children learned the associations from the practice problems. Differences in the effects of such associative knowledge on U.S. and Chinese children's fraction arithmetic performance are discussed, as are implications of these differences for educational practice. (PsycINFO Database Record (c) 2018 APA, all rights reserved).

Serial Adders with Overflow Correction

A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.