One-transistor Dynamic Random Access Memory Research Articles

Simulation of capacitorless DRAM based on polycrystalline silicon with a vertical underlap structure and a separated channel layer

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on polycrystalline silicon (poly-Si) with a vertical underlap structure and a separated channel layer was designed and analyzed. The memory performance was improved by the vertical underlap structure and the region separated into channel and storage layers. The vertical underlap structure suppressed the recombination rate by storing the holes in the isolated body and could be more easily fabricated than a conventional underlap structure. The thicknesses of the vertical underlap structure and storage region were optimized to enhance the memory performance. When the grain boundary (GB) is centrally located, the proposed 1T-DRAM demonstrates a retention time and sensing margin of 3.618 s and 29.93 μA μm−1, respectively. Even when the GB is in the worst position at T = 358 K, the memory still shows a retention time of 1.991 s and a sensing margin of 4.51 μA μm−1.

Bulk fin-type field-effect transistor-based capacitorless dynamic random-access memory with strong resistance to geometrical variations

In this study, a bulk fin-type FET (FinFET)-based capacitorless one-transistor dynamic random-access memory (1T-DRAM) was proposed. The fabrication process of the proposed 1T-DRAM was similar to that of a typical junctionless bulk FinFETs, except that the p-type doped body fin region operated as a charge storage region. The effects of the geometrical variations, such as the fin angle (θ fin) variation and line edge roughness (LER), which are inevitable in fabrication, on the transfer characteristics and memory performance of the proposed 1T-DRAM were studied. θ fin was varied from 90° to 80°, and 200 samples with the LER were analyzed. Results revealed that the transfer characteristics and memory performance were affected by geometrical variations. However, the proposed 1T-DRAM exhibited an excellent retention time in all cases because the charge storage region was separated from the region of operation.

Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing.

In this paper, we propose for the first time a self-refreshing mechanism in a junctionless field-effect transistor (JLFET) based on one-transistor dynamic random-access memory (1T-DRAM) with a silicon-on-insulator (SOI) structure. The self-refreshing mechanism continuously creates holes by appropriately generating impact ionization during the holding process through the application of an appropriate operation bias voltage. This leads to self-refreshing, which prevents the recombination of holes. When using the self-refreshing mechanism for the proposed device, the sensing margins were 15.4 and 12.7 μA/μm at 300 and 358 K, respectively. Moreover, the device achieved an excellent performance retention time of >500 ms, regardless of the temperature of the 1T-DRAM with a single gate. Furthermore, cell disturbance analysis and voltage optimization were performed to evaluate the in-cell reliability of the proposed device. It also showed excellent performance in terms of energy consumption and writing speed.

Simulation study of multi-source hetero-junction TFET-based capacitor less 1T DRAM for low power applications

A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The analysis of the three memory functions: Write, Hold and Read of 1T DRAM has been carried out using Synopsys TCAD simulations. A storage region of Ge material is used for the accumulation of holes/to store the charge carriers. The variation in length of Ge-storage region, under lap length (Lunder), and temperature is performed to analyse the DRAM performance. In the Write operation, the tunneling window reduces to 15 nm and holes can be easily stored in the Ge-storage region. In case of Hold1 and Read1 operations, the potential barriers are reduced by 0.24 eV, and 0.1 eV respectively. In the proposed multi-source TFET with 14 nm gate length, read current ratio i.e. IR1/IR0 of 4.4, retention time (RT) greater than 10 sec, and sense margin (SM) of 1.27 × 10−6 A/µm is achieved at room temperature. The proposed multi-source TFET based 1T DRAM is operating at very low gate voltages. Therefore, this device is well suited for low power applications.

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 μA/μm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley-Read-Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively.

1T DRAM with Raised SiGe Quantum Well for Sensing Margin Improvement

In this paper, a novel one-transistor dynamic random-access memory (1T DRAM) with a raised SiGe quantum well (QW) under one gate in the double-gate (DG) structure is proposed. The proposed structure can improve the poor performance of the retention time and sensing margin which is the problem of the conventional 1T DRAM. In write operation, the performance is improved through the band to band tunneling (BTBT) between body and drain and through valence band offset between SiGe and Si. Also by utilizing the physical barrier of oxide, read “1” retention time can be increased. The fabrication process is also proposed.

Design optimization of heterojunction 1T DRAM cell with SiGe body/drain for high performance

In this study, a heterojunction one-transistor (1T) dynamic random-access memory (DRAM) with SiGe body/drain has been proposed and its electrical characteristics have been investigated by technology computer-aided design simulation. The results reveal that the homojunction between body and drain with a narrow band gap material enhances not only retention characteristic but also write and erase efficiencies compared to those of the structure in which SiGe is only adopted at the body region. Consequently, the sensing margin of the optimized structure is ∼15.9 and ∼2.4 times larger than that of the Si and Si0.7Ge0.3-body 1T DRAM cells, respectively, with a retention time longer than 99 ms.

Design of a Capacitorless DRAM Based on Storage Layer Separated Using Separation Oxide and Polycrystalline Silicon

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon (Poly-Si) metal-oxide-semiconductor field-effect transistor (MOSFET) with a storage layer separated using a separation oxide was designed and analyzed using technology computer-aided design (TCAD). The channel and storage layers were separated using a separation oxide to improve the inferior retention time of the conventional 1T-DRAM, and we adopted the underlap structure to reduce Shockley-Read-Hall recombination. In addition, poly-Si, which has several advantages, including low manufacturing cost and availability of high-density three-dimensional (3D) memory arrays, is used to easily fabricate silicon-on-insulator (SOI)-like structures. Accordingly, we extracted memory performance by analyzing the effect of grain boundary (GB). The proposed 1T-DRAM achieved a sensing margin of 14.10 μA/μm and a retention time of 251 ms at T = 358 K, even in the existence of a GB.

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary’s influence

In this paper, a capacitorless one-transistor dynamic random access memory (1 T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor with the asymmetric dual-gate (ADG) structure is designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was used within the device due to its low fabrication cost and feasibility in high-density three-dimensional (3-D) memory arrays. We studied the transfer characteristics and memory performances of the single-layer ADG 1 T-DRAMs and the 3-D stacked ADG 1 T-DRAMs and analyze the reliability depending on the location and the number of grain-boundaries (GBs). The relative standard deviation (RSD) of the threshold voltages (Vth) is depending on the location and the number of GBs. The RSDs of the single-layer ADG 1 T-DRAM and the 3-D stacked ADG 1 T-DRAM are 1.58% and 0.68%, respectively. The RSDs of retention time representing the memory performances are 54.7% and 41%, respectively. As a result of the 3-D stacked structure, the averaging effect occurs, which greatly aids in improving the reliability of the memory performances as well as the transfer characteristics of 1 T-DRAMs depending on the influence of GBs. The proposed 3-D stacked ADG 1 T-DRAM helps implement a high-reliability single-cell memory device.

Predominance of Carrier Diffusion in Determination of Data Retention in One-transistor Dynamic Random-access Memory

One-transistor (1T) dynamic random-access memory (DRAM) has been widely studied for higher array density and obtaining three-dimensional (3-D) array stack viability by truncating the capacitor. However, its rather short retention time has been pointed out as a weak point compared with that of conventional one-transistor one-capacitor (1T1C) DRAM cell. The three dominating factors in determining the data retention in 1T DRAM can be sorted as diffusion, drift, and recombination, by which the programmed carriers are annihilated. In this study, out of those three major factors, the most predominant one is sought in the analytical and mathematical manners. It has been found that carrier diffusion has the key to modulation of the retention time of 1T DRAM and the other two factors are insignificantly small compared with diffusion. Error functions depending on both position and time were adopted to describe the distribution of programmed holes experiencing diffusion and drift in conjunction with solving the continuity equation. It has been concluded that carrier diffusion is the most dominant factor in determining the data retention in 1T DRAM, which suggests that proper ways of decelerating the carrier diffusion out of the channel be sought in optimally designing 1T DRAM cells.

Effect of Work-function Variation on Transfer Characteristics and Memory Performances for Gate-all-around JLFET based Capacitorless DRAM

In this study, we present variations in transfer characteristics and memory performances caused by work-function variation (WFV) in the metal gate of a one-transistor dynamic random-access memory cell based on a gate-all-around junctionless field-effect transistor (GAA-JLFET). To investigate the influence of WFV, we simulated 200 samples of GAA-JLFETs. The samples had different transfer characteristics depending on the metal grain granularity. In addition, we calculated and analyzed the mean and standard deviations for the transfer characteristics. Further, the memory performances were analyzed using two extreme cases with the highest and lowest threshold voltage (V<SUB>th</SUB>) as examples. When WFV was not considered, the current ratio was 108, and retention time was more than 10 ms. Meanwhile, when WFV was considered, the current ratio was 10² and 10⁴, and the retention time was reduced to 0.051 ms and 2.2 ms, respectively. These results showed that WFV affected not only the transfer characteristics in GAA-JLFET but also the memory performances; it could adversely affect the reliability of the memory device.

Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM.

A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level operation to replace 1T-1C-DRAM. To utilize 1T-DRAM as a memory device, we must understand its circuit-level operation, in addition to its device-level operation. Therefore, we studied the memory performance depending on device location in an array circuit and the circuit configuration by using the 1T-DRAM structure reported in the literature. The simulation results show various disturbances and their effects on memory performance. These disturbances occurred because the voltages applied to each device during circuit operation are different. We analyzed the voltage that should be applied to each voltage line in the circuit to minimize device disturbance and determine the optimized bias condition and circuit structure to achieve a large sensing margin and realize operation as a memory device. The results indicate that the memory performance improves when the circuit has a source line and the bias conditions of the devices differ depending on the write data at the selected device cell. Therefore, the sensing margin of the 1T-DRAM used herein can expectedly be improved by applying the proposed source line (SL) structure.

Reliability improvement of 1T DRAM based on feedback transistor by using local partial insulators

This paper proposes a one-transistor dynamic random-access memory (1 T DRAM) with local partial insulator (LPI) to increase data retention time. Proposed 1 T DRAM cell has improved retention characteristics because LPIs inhibit stored carrier movement with a high energy barrier. Definition of retention time in the proposed 1 T DRAM is introduced at hold “0” state. Device optimization with parameter variation is investigated with device simulation. As the barrier length increases, retention characteristics can be improved but it also causes a decrease in the I1/I0 current ratio. An increase in LPI length can improve the retention characteristics but reduce the I1/I0 current ratio. It was confirmed that the retention characteristics were improved as the hold bias was decreased. Finally, the retention characteristics were optimized when the LPI was precisely formed at the junction boundary.

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory.

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory's data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, "0" state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

L-Shaped Tunnel Field-Effect Transistor-Based 1T DRAM With Improved Read Current Ratio, Retention Time, and Sense Margin

In this article, an L-shaped tunnel field-effect transistor (LTFET)-based one-transistor dynamic random access memory (1T DRAM) with SiGe storage region was demonstrated through 2-D TCAD simulations. The SiGe storage is utilized to boost not only the sense margin (SM) but also the retention time (RT) in comparison to the previously published TFET-based 1T DRAMs. The simulation results reveal that the LTFET 1T DRAM acquired the SM of 6.2 μA/μm with RT of 1.7 s when 50-nm gate length was adopted at 27 °C, whereas at 85 °C, the LTFET 1T DRAM attains the SM and RT of 5.1 μA/μm and 290 ms, respectively. Furthermore, the LTFET 1T DRAM still attains the RT of 1.3 s at 27 °C when the gate length is scaled down to 20 nm. Thus, LTFET 1T DRAM exhibits a better gate length scalability in comparison to the counterpart TFET-based 1T DRAMs. In addition, we observed that the impact of ion irradiation on the proposed cell exhibits almost the same SM before and after the ion strike.

Analysis of Single Event Effects in Capacitor-Less 1T-DRAM Based on an InGaAs Transistor

In this work, the study of the single event effects (SEEs) in capacitor-less one-transistor dynamic random access memory (1T-DRAM) based on an indium gallium arsenide on insulator (InGaAs-OI) transistor is conducted for the first time. The electrical properties of the 90-nm device are numerically simulated to determine appropriate operation condition. The successful memory behaviors are observed due to the gate-induced drain leakage (GIDL) programming method. The impacts of different linear energy transfer (LET) values, high-energy particle (HEP) strike positions and directions, and HEP hitting moments on the memory performance are investigated via simulations. Unlike the conventional SOI device, the source and drain in 1T-DRAM cells are found to be sensitive to SEEs with a higher transient current. The single event upsets (SEUs) are found to occur only when the HEP hits the device at reading “0” state and holding state before read “0.” An increased read-out current is obtained after the HEP strike due to the GIDL- and SEE-induced accumulative floating holes. The related mechanisms are discussed in detail. These results and discussions are useful for the development of the SEE hardening of 1T-DRAM-based embedded memory for space applications in the future.

Performance Improvement of 1T DRAM by Raised Source and Drain Engineering

In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device simulation. The engineered device shows less short-channel effects (SCEs) and unwanted interband tunneling compared with the usual DG MOSFETs. As a 1T DRAM device, it demonstrates longer retention time ( T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ret</sub> ) and larger sensing margin (SM). The designed 1T DRAM achieves T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ret</sub> ~ 330 and ~ 200 ms at 27 °C and 85 °C, respectively, at 50-nm channel length. Also, the device shows higher current ratio and consumes low power (84.7 nW for write “1”) and energy ( 2.16×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> J for read “1” and 1.5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-17</sup> J for read “0” operations). Furthermore, it is revealed that low- κ spacer has an effect of increasing T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ret</sub> in the device.

Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances

In this work, a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor was designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was utilized within the device because of several advantages, including its low fabrication cost and the feasibility of its use in high-density three-dimensional (3D) memory arrays. An asymmetric dual-gate structure is proposed to perform the write “1” operation and achieve high retention characteristics. The proposed 1T-DRAM cell demonstrates a high sensing margin of 8.73 μA/μm and a high retention time of 704.4 ms compared to previously reported 1T-DRAMs, even at a high temperature. In addition, the effect of grain boundaries on the memory performance of the proposed device was investigated, and the results validated the excellent reliability of its retention characteristics even in the presence of grain boundaries (>64 ms at T = 358 K).

One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Effect Transistor with a Si/SiGe Heterostructure

This paper presents a one-transistor dynamic random-access memory (1T-DRAM) cell based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure for high-density memory applications. The proposed 1T-DRAM achieves the sensing margin using the difference in hole density in the body region between ‘1’ and ‘0’ states. The Si/SiGe heterostructure forms a quantum well in the body and reduces the band-to-band tunneling (BTBT) barrier between the body and drain. Compared with the performances of the 1T-DRAM with Si homo-structure, the proposed 1T-DRAM improves the sensing margin and retention time because its storage ability is enhanced by the quantum well. In addition, the thin BTBT barrier reduced the bias condition for the program operation. The proposed 1T-DRAM showed a high potential for memory applications by obtaining a high read current ratio at ‘1’ and ‘0’ states about 108 and a long retention time above 10 ms.