Analysis of Single Event Effects in Capacitor-Less 1T-DRAM Based on an InGaAs Transistor

Abstract

In this work, the study of the single event effects (SEEs) in capacitor-less one-transistor dynamic random access memory (1T-DRAM) based on an indium gallium arsenide on insulator (InGaAs-OI) transistor is conducted for the first time. The electrical properties of the 90-nm device are numerically simulated to determine appropriate operation condition. The successful memory behaviors are observed due to the gate-induced drain leakage (GIDL) programming method. The impacts of different linear energy transfer (LET) values, high-energy particle (HEP) strike positions and directions, and HEP hitting moments on the memory performance are investigated via simulations. Unlike the conventional SOI device, the source and drain in 1T-DRAM cells are found to be sensitive to SEEs with a higher transient current. The single event upsets (SEUs) are found to occur only when the HEP hits the device at reading “0” state and holding state before read “0.” An increased read-out current is obtained after the HEP strike due to the GIDL- and SEE-induced accumulative floating holes. The related mechanisms are discussed in detail. These results and discussions are useful for the development of the SEE hardening of 1T-DRAM-based embedded memory for space applications in the future.