One-dimensional Systolic Array Research Articles

Hardware acceleration of the novel two dimensional Burrows‐Wheeler Aligner algorithm with maximal exact matches seed extension kernel

Next-generation sequencing techniques have dramatically increased the amount of genomic data being sequenced, which calls for the acceleration of the alignment algorithms. This article proposes an FPGA-based accelerated implementation of the seed extension kernel of the Burrows–Wheeler alignment genomic mapping algorithm. The well-known Smith–Waterman algorithm is used during the seed extension to find the optimum alignment between the sequences. The state-of-the-art architectures in the literature use one-dimensional (1-D) systolic arrays to fill a similarity matrix, based on the best score out of all match combinations, mismatches and gaps are computed. The cells on the same anti-diagonal are computed in parallel in these architectures. We propose a novel 2-dimensional architecture in which all the cells on the same rows and the same columns are computed in parallel and, thereby, significantly accelerated the process. The similarity matrix cells are computed in two phases: (1) the calculation phase and (2) error compensation phase. The calculation phase roughly approximate the cell values and the approximation error is fixed up during the error compensation phase. Our simulation results show that the proposed architecture can be up to 718x and 1.7x faster than the software execution and the 1-D systolic arrays, respectively.

A truly two-dimensional systolic array FPGA implementation of QR decomposition

We have implemented a two-dimensional systolic array QR decomposition on a Xilinx Virtex5 FPGA using the Givens rotation algorithm. QR decomposition is a key step in many DSP applications including sonar beamforming, channel equalization, and 3G wireless communication. Compared to previous work that implements Givens rotations using a one-dimensional systolic array, our implementation uses a truly two-dimensional systolic array architecture. As a result, latency scales well for larger matrices. In addition, prior work avoids divide and square root operations in the Givens rotation algorithm by using special operations such as CORDIC or special number systems such as the logarithmic number system (LNS). In contrast, our design uses straightforward floating-point divide and square root implementations, which makes it easier to be used within a larger system. In our design, the input matrix size can be configured at compile time to many different sizes, making it easily scalable to future large FPGAs or over multiple FPGAs. The QR module is fully pipelined with a throughput of over 130MHz for the IEEE single-precision floating-point format. The peak performance for a 12 × 12 input matrix is approximately 35 GFLOPs.

A parallel algorithm for generating chain code of objects in binary images

This paper addresses parallel execution of chain code generation on a linear array architecture. The contours in the proposed algorithm are viewed as a set of edges (or contour segments) that can be traced by a top-down contour tracing method to generate the chain codes for the outer and inner object contours. A parallel algorithm that contains the chain code generating rules and operations needed is also described, and the algorithm is mapped onto a one-dimensional systolic array containing ⌈ 1 2 (N+1)⌉ processing elements (PEs) to devise this architecture. The architecture extracts the contours of objects and quickly generates the corresponding chain codes after the image data in all rows are inputted in a linear fashion. The total processing time for generating the chain codes in an N× N image is O(3 N). By doing so, the real-time requirement is fulfilled and its execution time is independent of the image content. In addition, a partition method is developed to process an image when the parallel architecture has a fixed number of PEs; say two or more. The total execution time for an N× N image by employing a fixed number of PEs is N( N+1)/ M+2( M−1), when M is the fixed number of PEs.

Digital hardware realization of a recurrent neural network for solving the assignment problem

The digital hardware realization of a recurrent neural network for solving the assignment problem is presented. The design is based on an analog neural network and is mapped to a one-dimensional systolic array for parallel processing. The processing elements are connected with a ring topology that reduces the overhead in controlling the pipeline. The design was simplified by exploiting regularities in the data to eliminate the need for multipliers and dividers in hardware implementation. The results of implementation and verification based on field programmable gate array device show the feasibility of the digital neural network approach to the assignment problem.

A unified systolic array design for kernel functions of video compression

In video compression, some kernel functions such as block matching, discrete wavelet transform, vector quantization, etc., are of prime essential, but with a large amount of computation. Recently, many systolic array architectures have been designated for performing each of those functions in real time. In fact, many kernel functions contain the similar computational procedure. If we dissect these functions into the basic matrix-vector product forms, a unified design for them becomes feasible. In this brief, by carefully extracting the common computation component, a unified one-dimensional systolic array design that can perform at least the above three functions is presented. In this design, the input data is serial-in to save the amount of pins required, and the data flow are carefully arranged to simplify the interconnection between computation components. When 64 registers are in the on-chip memory, our design can perform three typical functions: (1) the full-search block matching with block size 16/spl times/16 and the search range (-8,7); (2) the 2-D Harr transform with block size 8/spl times/8; and (3) the vector quantization with input vector size 4/spl times/4 and codebook size 256. Since the unified architecture reduces hardware costs, and has a regular hardware structure, it is suited for VLSI implementation for video/image compression applications that require all the functions.

A systolic array implementation of the Feng-Rao algorithm

An efficient implementation of a parallel version of the Feng-Rao algorithm on a one-dimensional systolic array is presented in this paper by adopting an extended syndrome matrix. Syndromes of the same order, lying on a slant diagonal in the extended syndrome matrix, are scheduled to be examined by a series of cells simultaneously and, therefore, a high degree of concurrency of the Feng-Rao algorithm can be achieved. The time complexity of the proposed architecture is m+g+1 by using a series of t+[g-1/2]+1, nonhomogeneous but regular, effective processors, called PE cells, and g trivial processors, called D cells, where t is designed as the half of the Feng-Rao bound. Each D cell contains only delay units, while each PE cell contains one finite-field inverter and, except the first one, one or more finite-field multipliers. Cell functions of each PE cell are basically the same and the overall control circuit of the proposed array is quite simple. The proposed architecture requires, in total, t+[g-1]+1 finite-field inverters and (t+[(g'1)/2])(t+[(g-1)/2]+1)/2 finite-field multipliers. For a practical design, this hardware complexity is acceptable.

An Orthogonal Time-Frequency Extraction Approach to 2D Systolic Architecture for 1D DFT Computation

An expandable two-dimensional systolic array consisting of N homogeneous processing elements in a rectangular sturcture to compute the one-dimensional DFT transform is proposed. DFT of size N = M^2 can be computed in 2M steps of pipelined operations, achieving the optimal Area–Time complexity of AT^2 e O(N^2). The architecture is based on a new approach that exploits the symbiosis between the one-dimensional systolic arrays of Kung [6] and Chang [7]. After a two-dimensional formulation with Common Factor Algorithm, recursive time and frequency extractions are applied to the column and row transforms respectively. Twiddle factor multiplication is integrated gracefully into the row recursion. The rearrangement of the input data enables the recursive operations to be pipelined orthogonally in the “dual-mode” processing elements. The proposed array structure is modular and expandable. A DFT of size 2^LN can be readily computed with 2^L N-size arrays abutted together without reconfiguration. VHDL modules have been written and simulated successfully for the proposed architecture.

Parallel processing architecture for the quasi-Newton method based on BFGS using one-dimensional systolic arrays

Parallel processing architecture for the quasi-Newton method based on BFGS using one-dimensional systolic arrays

VLSI FOR MOMENT COMPUTATION AND ITS APPLICATION TO BREAST CANCER DETECTION

Moment has been one of the most popular techniques for image processing, pattern classification and computer vision. In this paper, we propose two VLSI architectures for computing the regular (geometric) moments and central moments. First, a one-dimensional systolic array is presented. In this architecture, a dynamic time delay controller is used for obtaining the correct data flow. It takes max(p, q)×n+n+2 time units to compute the moments of order ( p+ q). If there are k images, the computational time will be k[ max(p, q)×n+n+2] . Second, a two-dimensional architecture is presented. It takes n+ n+ n−1+2+1=3 n+2 time units to compute the moments of order ( p+ q). If there are k images, the computational time will be ( k−1)×2 n+3 n+2=2 nk+ n+2. Thee proposed approaches are much faster than the existing ones. If a uniprocessor is used, the time complexity is (p+q) n 2 , and if there are k images, the computational time will be k(p+q) n 2 . Finally, a VLSI architecture is presented for calculating the central moments. In this architecture, 3× n processing elements are used for calculating m 00, m 01, and m 10 . The results are sent to a two-dimensional structure for computing central moments. It takes 2n+3+ max(p, q)+2+n+n−1+1=4n+ max(p, q)+5 time units to finish the calculation of the central moments. The important issue of VLSI design, algorithm partition, is also addressed. The basic idea of this paper can be extended to compute other kinds of moments easily. We have applied the moments for extracting the features of breast cancer biopsy images and classified them using neural networks. The 100% classification rate has been achieved.

Systolic decoder for burst error-correcting codes

The author develops a new systolic architecture for the decoding of single-burst error-correcting cyclic codes (SBECCC). The well known decoding procedure for these codes, based on the error-trapping technique, is expressed by means of uniform recurrence equations to be implemented using systolic arrays. The decoder uses the generator polynomial of the code. For an (n, k) SBECCC, with a burst-error correcting capability l, the decoder consists of (n + k – 1) cells arranged into a serial-in serial-out one-dimensional feed-forward systolic array. The decoder has the following advantages: it does not contain any feedback connection; it is easily reconfigurable for variable code parameters n, k and l and changes in the choice of the generator polynomial.

Design of fast motion estimation algorithm based on hardware consideration

Most fast block-matching motion estimation (BMME) algorithms are designed to minimize the search positions (or checking points) in a given search range in order to speed up the computation. In this paper, we introduce a fast BMME algorithm based on the consideration of hardware implementation. We use a one-dimensional (1-D) systolic array as the basic computing engine. In order to utilize this engine efficiently, we process several adjacent checking points, called checking vector, simultaneously. We propose a checking-vector-based search strategy and show that it can achieve a better algorithmic performance and can be very cost-effective in terms of hardware implementation for low bit-rate video applications.

Reconfigurability and reliability of systolic/wavefront arrays

The authors study fault-tolerant redundant structures for maintaining reliable arrays. In particular, they assume that the desired array (application graph) is embedded in a certain class of regular, bounded-degree graphs called dynamic graphs. The degree of reconfigurability (DR) and DR with distance (DR/sup d/) of a redundant graph are defined. When DR and DR/sup d/ are independent of the size of the application graph, the graph is finitely reconfigurable (FR) and locally reconfigurable (LR), respectively. It is shown that DR provides a natural lower bound on the time complexity of any distributed reconfiguration algorithm and that there is no difference between being FR and LR on dynamic graphs. It is also shown that if both local reconfigurability and a fixed level of reliability are to be maintained, a dynamic graph must be of a dimension at least one greater than the application graph. Thus, for example, a one-dimensional systolic array cannot be embedded in a one-dimensional dynamic graph without sacrificing either reliability or locality of reconfiguration.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The synthesis of control signals for one-dimensional systolic arrays

This paper presents a method for the synthesis of control signals for one-dimensional systolic arrays from a program expressed as a set of uniform recurrence equations ( source UREs). The basic idea underlying the synthesis of control signals is to distinguish different types of computation prescribed by the source UREs with another set of uniform recurrence equations ( control UREs). To obtain one-dimensional systolic arrays with a description of both data and control signals, one simply applies the standard space-time mapping technique to the source and control UREs.

A cascadeable pipeline Fast Fourier Transform switch with built-in self-test

A pipeline Fast Fourier Transform (FFT) switch with built-in self-test is described. The pipeline FFT, a one-dimensional systolic array, is composed of complex butterflies and FFT switches. The FFT switches are cascadeable and can support the implementation of a radix-2 pipeline FFT of up to 8192 points. The 10 000 gate ASIC device is fabricated in 1.5μm HCMOS gate array technology, and supports a throughput of 25 Mwords s −1.

Comparison of tree and straight-line clocking for long systolic arrays

Achieving efficient and reliable synchronization is a critical problem in building long systolic arrays. This problem is addressed in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. Analytic bounds are presented for the probability of failure, and an examination is made of the tradeoffs between reliability and throughput in both schemes. The basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes preferable to straight-line clocking. >

Systolic algorithms for computational geometry problems — A survey

With the recent development of a rich variety of parallel computer architectures, much attention has been paid to the study of parallel computational geometry. In this paper we put the focus on systolic computational geometry algorithms among those algorithms being developed rapidly in recent years for the various kinds of parallel processors. Our paper gives a survey of recent studies on systolic computational geometry algorithms We show that most of the fundamental geometrical problems can be solved in linear-time by conventional one-dimensional systolic arrays proposed by Kung et al. This paper also includes many new results and some open problems for which we have no linear-time systolic algorithms.

Array architectures for block matching algorithms

A description is given of VLSI architectures for block-matching algorithms utilizing systolic array processors. A well-known mapping procedure has been applied to derive the array processors from the algorithm. Examples of two- and one-dimensional systolic arrays are presented. The transistor-count of the architectures using presently available CMOS technology and their maximum processable frame rates for real-time computation of video signals have been estimated. >

Efficient one-dimensional systolic array realization of the discrete Fourier transform

A one-dimensional systolic array realizing the discrete Fourier transform (DFT) of nonstop input sequences is presented. Two arrays having different output schemes, i.e. pipelined and bus-oriented output paths, are introduced. Both arrays require N cells and take N clock cycles to produce a complete N-point DFT. The latency time for the pipeline scheme is twice that of the bus-oriented scheme. For both arrays, a continuous flow of input vectors is allowed and no idle period is required between successive vectors. The array coefficients are static and thus stored-product ROMs (read-only memories) can be used in place of multipliers to limit cost as well as eliminate errors due to coefficient quantization.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On Efficient Simulations of Systolic Arrays by Random-Access Machines

We give efficient simulations of systolic arrays by unit-cost random-access machines (RAM’s). For example, we show that a one-dimensional systolic array operating in linear time can be simulated by a RAM in $O({{n^2 } / {\log ^2 n}})$ time. For the case of a two-dimensional systolic array, the simulation time is $O({{n^3 } / {\log ^{{3 / 2}} n}})$.

The area-time complexity of a VLSI digital filter using residue number systems

Combining the Residue Number System (RNS) as a computational tool and VLSI as a fabrication medium promises to provide modular and cost efficient implementation of many digital signal processing algorithms. In this paper, a one-dimensional systolic array is used as a system structure to implement a finite impulse response (FIR) filter based on RNS. The building block unit of this structure is a multi look-up table module having two possible configurations. For this architecture a complexity analysis has been evaluated in terms of area and time. This analysis is based on RNS computational model. The structure is completely pipelined; that is, the throughput rate (bits/sec) is independent of the filter order. The upper bound of the system cycle ( T cycle) is 0 ( n/log n).