One-bit Cell Research Articles

Using Novel One-Bit ADC to Design n-Bit ADC

This work presents two novel styles for designing n-bit analog to digital converter (ADC). Each of the proposed ADCs is built using novel one-bit cell. The novel cell produces single output bit as a response to an input voltage, in addition, it outputs another analog voltage. The generated analog voltage is used again as an input to the to generate one more bit, and new analog voltage, and so on. The proposed n-bit ADC is built using the novel one-bit cell in two different styles. One design style, by connecting n ADC cells together to construct n-bit ADC that produces parallel binary outputs. The other design style realizes the n-bit ADC using single ADC cell and outputs n-bit serially. In both ADC designs introduced in this work, modularity was the main design parameter. The two different n-bit ADCs have been simulated. The first n-bit ADC with parallel outputs produces clean outputs at 50MS/s, and the other ADC design shows clean serial bits at 5KS/s.

New CMOS circuit implementation of a one-bit full-adder cell

A new mirror CMOS circuit implementation of a one-bit full-adder cell is proposed. Using CMOS technology provides zero static power consumption and the freedom from fractional voltage levels at the internal nodes (no voltage recovery is needed). The solution proposed is shown to be superior in carry speed to any alternative CMOS implementation reported so far, and should therefore be suitable for building high-speed multibit adders.

A Low‐Temperature‐Grown Oxide Diode as a New Switch Element for High‐Density, Nonvolatile Memories

A one-bit cell of a general nonvolatile memory consists of a memory element and a switch element. Several memory elements have been tried given that any bistable states, that is, two charging states, two spin states, or two resistance states, can be used for a memory element. On the other hand, silicon-based transistors have been the most popularly used switch element. However, silicon-based transistors do not conform to high-density, nonvolatile memories with three-dimensional (3D) stack structures due to their high processing temperatures and the difficulty of growing high-quality epitaxial silicon over metals. Here, we show a low-temperaturegrown oxide diode, Pt/p-NiOx/n-TiOx/Pt, applied as a switch element for high-density, nonvolatile memories. The diode exhibits good rectifying characteristics at room temperature: a rectifying ratio of 10 at ± 3 V, a forward current density of up to ∼ 5×10 A cm, an ideality factor of 4.3, and a turn-on voltage of 2 V. Furthermore, we verify its ability to allow and deny access to the Pt/NiO/Pt memory element with two stable resistance states. Under the forward-bias condition, we could access the memory element and change the resistance state, although access was denied under the reverse bias condition. This one-diode/one-resistor (1D/1R) structure could be a promising building block for high-density, nonvolatile random-access memories with 3D stack structures. A p–n diode, like a transistor, is a fundamental circuit element for thin-film electronics. Until now, epitaxial silicon was most frequently used to fabricate p–n diodes in electronic devices with planar structures. However, to increase device density further, we require p–n diodes that are applicable to devices with 3D stack structures. Epitaxial silicon-based p–n diodes cannot be fabricated with stack structures as it is difficult to grow on a metal layer and high processing temperatures are required. On the other hand, although amorphous silicon allows for lower processing temperatures, it does not provide the required semiconducting performance. Therefore, to realize high-density electronic devices with 3D stack structures, we need new p–n diodes composed of semiconducting materials with low processing temperatures and high performance. In particular, new p–n diodes with low processing temperatures and high performance are indispensable to high-density, nonvolatile random-access memory devices. By replacing a transistor with a simpler diode as a switch element, there exists the possibility of producing memory cells with cross-point structures composed of bit lines and word lines perpendicular to each other, with a memory element lying between them. Theoretically, by utilizing this cross-point structure, the cell size can be scaled down to 4F (F: feature size used for patterning the cell), which is the smallest cell size attainable in nonvolatile memories with planar structures. Furthermore, by fabricating 3D stacks of the cross-point structure, the effective cell size can be scaled down to 2F, 1F, and so on. A common issue in realizing a cross-point structure is the availability of a thin-film diode with the high rectifying ratio and current density required for the switch element to access the memory element. Oxide based p–n diodes are good candidates to provide solutions to the issues associated with Si-based diodes. Most oxides, such as TiO2, [4] ZrO2, [5] ZnO, and indium tin oxide (ITO), are well-known n-type semiconductors that are characterized by the electron-transport properties of oxygen vacancies. As NiOx is a well-known p-type semiconductor beC O M M U N IC A IO N