On-wafer Scattering Parameter Measurements Research Articles

Accurate and Efficient Self-Calibration Algorithm of Broadband On-Wafer Scattering-Parameter Measurements for Production Test Applications Up to 110 GHz

This paper presents an accurate and efficient on-wafer calibration algorithm of broadband scattering-parameter measurements for radio-frequency integrated circuit production test applications. Three on-chip calibration standards with the same probe positions as those of the devices under test (DUTs) were designed to take advantage of fixed probe heads in the x–y directions during calibration and measurements. In addition, three on-chip standards—a series resistor and a shunt resistor (both of which have an offset line segment) as well as a transmission line (TL)—do not have to be characterized in advance, and the measurement reference impedance can be acquired further though self-calibration without an impedance-standard substrate (ISS). Simulation studies and experimental confirmation were conducted on GaAs substrates, from 2 to 110 GHz, in addition to comparisons of the multiline thru-reflect-line (TRL) calibration results.

Generalization and Reduction of Line-Series-Shunt Calibration for Broadband GaAs and CMOS On-Wafer Scattering Parameter Measurements

This paper presents generalization and reduction of the line-series-shunt (LST) calibration technique, including generic parasitic treatments on the series/shunt standards and number reduction of calibration standards, for broadband GaAs and CMOS on-wafer scattering parameter ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameter) measurements. The series/shunt standards are modified with additional transmission-line (TL) sections on both the left and right sides to directly solve the five calibration parameters, namely, TL propagation constant, series impedance, shunt admittance, series parasitic admittance, and shunt parasitic impedance. This approach relaxes the constraint on the series/shunt standards that may not satisfy the plain lossy TL assumption in the parasitic evaluations. The calibration can be further reduced by only two standards if the lossy TL models for the series/shunt standards are satisfied. These points are examined by a microstrip test structure built on GaAs and CMOS technologies, with verification of an independent thru-reflect-line calibration.

Microwave measurements and systematic circuit-model extraction of nanowire metal semiconductor field-effect transistors

We present detailed on-wafer scattering-parameter measurements and equivalent circuit modeling of a metal semiconductor field-effect transistor (MESFET) that incorporates a GaN nanowire (NW). A systematic procedure is established to extract intrinsic model parameters by removing extrinsic parameters of the NW under different bias conditions. All parameters are first determined from analytic formulas that establish their relationship to measured impedance and admittance parameters. The analytically determined parameters are then processed in a numerical fitting program and a circuit simulator for minimizing the difference between the modeled data and the experimental data. For demonstration, the proposed framework is applied to a GaN NW MESFET with 1.5 μm long gate up to 10 GHz. Its transconductance is estimated to be 16.6 μS, the transit time is estimated to be 9.8 ps and the maximum frequency of oscillation is about 16 GHz.

Radio-Frequency Study of Dopant-Segregated n-Type SB-MOSFETs on Thin-Body SOI

We present a detailed direct current and radiofrequency study of fully depleted dopant-segregated Schottky barrier (SB) MOSFETs on thin-body Silicon-on-Insulator. On-wafer scattering-parameter measurements of n-type NiSi source/drain SB-MOSFETs provide an in-depth understanding of key device parameters (transconductances and capacitances) as a function of the implanted arsenic dose, i.e., different SB height. Devices with 80-nm-channel length show a high ON current of 1150 mA/mm and exhibit a unity-gain cutoff frequency of fT = 140 GHz.

Low-Loss and Wideband Package Transitions for Microwave and Millimeter-Wave MCMs

This paper presents high-performance flip-chip, through-substrate via and board-level BGA transition designs applicable in microwave and millimeter-wave multichip module (MCM) assemblies. Full-wave electromagnetic analysis was performed to achieve optimized transition structures. Interconnection test structures were fabricated in ceramic substrates and their performance was validated using on-wafer scattering parameter measurements. Both the flip-chip transition and the through-substrate via transition with a height of 800 mum exhibited return losses better than 25 dB and 20 dB, respectively, with low transmission losses up to 50 GHz. Furthermore, the wideband board-level BGA transition with a standoff height of 500 showed low insertion loss (< 0.5 dB) over a wide frequency range, from direct current (dc) up to 32.5 GHz.

An accurate photonic capacitance model for GaAs MESFETs

A new set of pseudoempirical equations is presented in order to simulate the optical and bias dependencies of GaAs MESFET junction capacitances, which is valid for the whole I-V plane. The variations induced in the small-signal equivalent circuit by the optical illumination are extracted from on-wafer scattering parameter measurements. New linear and quasi-logarithmic variations versus the incident optical power are shown for gate-drain and gate-source (Cgd and Cgs) capacitances. Furthermore, experimental results are in very good agreement with the simulated values for a wide range of optical power and bias conditions. Large signal MESFET models show a better fit with measured S-parameters than those previously published, leading to a greater degree of confidence in the design of photonic monolithic microwave integrated circuits.