On-chip Wireless Interconnects Research Articles

Polarization Effect on the Performance of On-Chip Wireless Optical Point-to-Point Links

Optical on-chip wireless interconnection is an emerging technology that aims to overcome the communication bottleneck in computing architectures and in which multiple processing units are exploited for data-intensive applications. In this work, we propose an integrated dielectric Vivaldi antenna, which exhibits the same gain performances for both TE and TM input polarizations. Point-to-point on-chip communication links between two Vivaldi antennas are analyzed. Moreover, the effect of wave polarization on the link performances is numerically studied in on-chip multilayer structures in connection with the multilayer characteristic parameters, i.e., cladding layer thickness and refractive index. The numerical results show that, with the same antenna gain, TM polarization is affected by lower propagation losses when suitable cladding layer thickness and refractive index are considered.

TSV‐based antenna for on‐chip wireless communication

On-chip wireless interconnects provide signal broadcasting and link shortcuts for improved latency and throughput, useful considering the increase of the number of processing elements on a chip. In this work, a through-silicon via antenna (TSV_A) for on-chip wireless communication is proposed. TSV_A significantly improves the wireless interconnect performance over current solutions of on-chip antennas, which occupy a large area of the chip and are not capable of far-reaching transmission. Printed circuit board (PCB) prototypes are designed and fabricated to validate the proposed TSV_A. The PCB prototype of the TSV_A has an insertion loss of 5-10 dB at a distance of similar or equal to 20 mm, measured in PCB and validated with high fidelity 3D finite element method simulation results. TSV_A has improved path loss, smaller size, and lower manufacturing costs due to the well-established TSV fabrication process for 3D-ICs. Projections for an on-chip 3D-IC operation indicate up to 40 dB improved signal strength compared to other on-chip antennas, with an insertion loss of similar or equal to 3-5 dB up to a 30 mm distance.

Unified Testing and Security Framework for Wireless Network-on-Chip Enabled Multi-Core Chips

On-chip wireless interconnects have been demonstrated to improve the performance and energy consumption of data communication in Network-on-Chips (NoCs). However, the wireless interfaces (WIs) can be defective, rendering these broken links severely affect the performance. This makes manufacturing test of the WIs critical. While analog testing of the transceivers is possible, such methodologies are impractical in a Wireless NoC (WiNoC) due to large overheads. In addition to testing, security is another prominent challenge in WiNoCs, as the security breach can happen due to embedded hardware Trojans or through external attacker exploiting the wireless medium. The typical security measures used in general wireless networks are not practical in a WiNoC due to unique network architectures and performance requirements of such a system. However, both testing and security defense can potentially leverage a basic monitoring framework which, can detect malfunctions or anomalies. Based on this idea, we propose a unified architecture for testing and attack detection and protection of on-chip wireless interconnects. We adopt a Built-In-Self Test (BIST) methodology to enable online monitoring of the wireless interconnects which can also be reused for monitoring the security threats. We focus on manufacturing defects of the WIs for testing and persistent jamming attack for the security measures, as this kind of attack is most likely on wireless communication systems. The BIST methodology is capable of detecting faults in the wireless links with a low aliasing probability of 2.32× 10 −10 . Additionally, the proposed unified architecture is able to detect the persistent jamming with an accuracy of 99.87% and suffer < 3% communication bandwidth degradation even in the presence of attacks from either internal or external sources.

Characterisation of on‐chip wireless interconnects based on silicon nanoantennas via near‐field scanning optical microscopy

Recently, a novel Photonic-Integrated Circuit (PIC) paradigm based on the use of a new kind of ultra-directive, low-loss, highly efficient and broadband silicon nanoantenna has enabled the first demonstration of an on-chip wireless interconnect, with potential applications in reconfigurable networks and lab-on-a-chip systems. Despite the fact that the far-field properties of these nanoantennas have been widely studied, their near-field behaviour stays unexplored. Here, the authors study this feature through scanning near-field optical microscopy (SNOM). For this purpose, the authors design and characterise an on-chip two-port wireless link using a tailored SNOM. The conducted near-field measurements will be useful to improve the design of these integrated photonic devices with potential impact on a variety of applications, from biosensing to optical communications.

Evaluation of wireless network-on-chip architectures with microchannel-based cooling in 3D multicore chips

Three-dimensional multicore Integrated Circuits (3D ICs) with Network-on-Chip (NoC) based interconnections provide promising solutions to the challenges of footprint, device density and energy cost of on-chip communication. However, the increase in power density in 3D ICs due to reduced footprint aggravates the thermal issues in the chip. Liquid cooling through microfluidic channels can provide cooling capacities required for effective management of chip temperatures in 3D ICs. However, pumping liquid through the microchannels can cause high pressure-drops causing structural instability in the chip. In order to reduce the pressure drops and provide adequate cooling capability, the height and width of the microchannels needs to be increased. This reduces the available floor area of the 3D IC to place and route Through Silicon Vias (TSVs) for data signals through the microchannel walls making the co-design of microchannels and TSVs challenging. Hence, in this paper we evaluate the advantages and discuss the trade-offs of realizing the vertical interconnects for data communication across the cooling layers with on-chip wireless interconnects. We present optimal design for microchannels for cooling 3D multicore chips from a combined perspective of thermal efficiency, flow rate and pressure drop. Based on these designs we discuss the potential of wireless interconnects and demonstrate that a 3D wireless NoC is capable of establishing data communication across the cooling layers with lower energy consumption.

Interference-Aware Wireless Network-on-Chip Architecture Using Directional Antennas

Wireless Network-on-Chip (WiNoC) has been recently introduced for addressing the scalability limitations of conventional multi-hop NoC architectures. Existing WiNoC architectures generally use millimeter-wave antennas without significant directional gains, along with token passing protocol to access the shared wireless medium. This limits the achievable performance benefits since only one wireless pair can communicate at a time. It is also not practical in the immediate future to arbitrarily scale up the number of non-overlapping channels by designing transceivers operating in disjoint frequency bands in the millimeter-wave spectrum commonly adopted for on-chip wireless interconnects. Consequently, we explore the use of directional antennas whereby multiple wireless interconnect pairs can communicate simultaneously. However, concurrent wireless communications can result in interference. This can be minimized in NoC by optimal placement of wireless interfaces (WIs) to maximize performance while minimizing interference. To address this, we propose an interference-aware WIs placement algorithm with routing strategy for WiNoC architecture by incorporating directional planar log-periodic antennas (PLPAs). This directional wireless network-on-chip (DWiNoC) architecture enables point-to-point links between transceivers and hence multiple wireless links can operate at the same time without interference.

A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors

With the rise of chip multiprocessors, an energy-efficient communication fabric is required to satisfy the data rate requirements of future multi-core systems. The Network-on-Chip (NoC) paradigm is fast becoming the standard communication infrastructure to provide scalable inter-core communication. However, research has shown that metallic interconnects cause high latency and consume excess energy in NoC architectures. Emerging technologies such as on-chip wireless interconnects can alleviate the power and bandwidth problems of traditional metallic NoCs. In this paper, we propose A-WiNoC , a scalable, adaptable wireless Network-on-Chip architecture that uses energy efficient wireless transceivers and improves network throughput by dynamically re-assigning channels in response to bandwidth demands from different cores. To implement such adaptability in our network at run-time, we propose an adaptable algorithm that works in the background along with a token sharing scheme to fully utilize the wireless bandwidth efficiently. Since no wireless NoC design has been completely realized with current technology, we describe technology trends in designing energy-efficient wireless transceivers with emerging technologies. We compare our proposed A-WiNoC to both wireless and wired topologies at 64 cores, with results showing a 1.4-2.6 $\times$ speedup on real applications and a 54 percent improvement in throughput for synthetic traffic. Using Synopsys Design Compiler, our results indicate that A-WiNoC saves 25-35 percent energy over other state-of-the-art networks. We show that A-WiNoC can scale to 256 cores with an energy improvement of 21 percent and a saturation throughput increase of approximately 37 percent.

Design Methodology for a Robust and Energy-Efficient Millimeter-Wave Wireless Network-on-Chip

Wireless Network-on-Chip (WiNoC) architectures with CMOS compatible millimeter-wave (mm-wave) transceivers can achieve significant improvements in energy-efficiency in on-chip data transfer for multicore chips. A token based medium access mechanism is used in mm-wave WiNoC architectures to enable a distributed utilization of the available wireless bandwidth among multiple transmitters. However, on-chip wireless interconnects can suffer from high rates of failures due to challenges in design and manufacturing. Consequently, the token-passing mechanism can fail and significantly degrade the potential benefits of this novel interconnect technology. In this paper, we establish a cross-layer robust and failure-resistant design methodology for WiNoC architectures. By optimizing the WiNoC topology and complementing it with a robust token management scheme and error correction codes, we propose to design a failure-resistent WiNoC. Through system-level simulations, we demonstrate that the proposed design can mitigate the effect of various types of failures of the wireless fabric in WiNoC architectures without compromising the energy-efficiency.

Efficient Design of Integrated Antennas on Si for On-Chip Wireless Interconnects in Multi-Layer Metal Process

In this study it has been shown that the transmission gain of an integrated dipole antenna on a Si chip used for an on-chip wireless interconnect is drastically reduced in a multi-layer metal interconnect scheme when a second metal layer is placed above the antenna at the usual interlayer metal distance. The best way to preserve high gain of the integrated antenna in such a multi-layer metal process is to design an antenna with excitation vertically through the Si substrate. In the presence of the upper metal layers, the vertically excited field mode propagating through the Si substrate does not cause any significant reduction in the power transmission of the antenna. Simulations of the structures have been carried out using the ANSOFT high frequency structure simulation (HFSS) program employing the three dimensional finite element method. A simple analytical model has also been developed, and the results are presented for comparison.

Effect of High-Resistivity Si Substrate on Antenna Transmission Gain for On-Chip Wireless Interconnects

Characterization of small integrated dipole antennas on high-resistivity Si substrates for use in on-chip wireless interconnection was performed and results were compared with those obtained by 3-dimensional (3D) finite-element simulation. The integrated antennas on standard P-type Si substrates with resistivities of 10 Ω·cm, 79.6 Ω·cm, 132 Ω·cm and 2.29 kΩ·cm, and one high-energy proton-implanted Si substrate were measured. When antenna length was 3.0 mm and antenna distance was 3.0 cm on a 10-Ω·cm-resistivity Si substrate, the antenna transmission gain was -43 dB. The antenna transmission gain was improved to -24 dB on the 2.29 kΩ·cm Si substrate. By using high-resistivity Si substrates, signal transmission via integrated antennas becomes possible.

Characteristics of Integrated Antenna on Si for On-Chip Wireless Interconnect

We have performed the detailed characterization of small size integrated dipole antenna on Si for use in on-chip wireless interconnection and compared the measured characteristics with results obtained by 3-D finite element simulation. Basic characteristics such as the effects of antenna length, distance and rotation angle on the transmission gain of the integrated antenna are examined. The measured transmission gain of approximately -54 dB at a distance of 1 cm for a 0.02 mm2 dipole antenna at 20 GHz showed the feasibility of using the integrated dipole antenna for wireless clock distribution in future ultra LSI (ULSI) chips at frequencies of ∼20 GHz or higher. We have also shown that it is possible to minimize any reduction in transmission gain due to the interference from the local interconnect metal lines by choosing the proper layout.

High transmission gain integrated antenna on extremely high resistivity Si for ULSI wireless interconnect

We have demonstrated the highest transmission gain integrated dipole antenna on Si reported so far, to use as an integrated antenna for the purpose of ULSI on-chip wireless interconnection. A 2-mm long and 10-/spl mu/m wide dipole antenna pair at a distance of 1 cm shows a transmission gain of -36.5 dB at 18 GHz, which is 20 dB higher than the previously reported gain. This large increase in gain is achieved by proton implantation on the Si substrate, which increased the resistivity from 10 /spl Omega/-cm to 0.1 M/spl Omega/-cm. It is also found that transmission gain can be maximized for a given resistivity by optimizing the Si substrate thickness or by inserting a low-k dielectric layer below the substrate.