On-chip Temperature Variations Research Articles

Ant Colony Optimization-Based Thermal-Aware Adaptive Routing Mechanism for Optical NoCs

Optical networks-on-chip (NoC) based on silicon photonics has been proposed as an emerging on-chip communication infrastructure of chip multiprocessors. However, due to thermal sensitivity of optical devices under on-chip temperature variations, significant thermal-induced optical power loss would offset the benefit of optical NoCs in power efficiency. In this work, we propose a thermal-aware adaptive routing scheme based on ant colony optimization (ACO) to alleviate the thermal issue. The proposed ACO-based routing scheme applies the ACO method to formulate and optimize the routing decisions with the objective of reducing optical power loss under temperature variations. The traditional implementation of the ACO-based routing scheme requires a table in each node to keep and update pheromone, and the table size increases linearly with the number of nodes in the network. To avoid the table overhead, we further propose an approximate ACO-based routing (AACO) scheme based on linear regression. A case study on an <inline-formula> <tex-math notation="LaTeX">$8\times 8$ </tex-math></inline-formula> mesh-based optical NoC under a series of synthetic traffic patterns and real applications shows that the proposed routing schemes are able to select near-optimal paths under varying on-chip temperature variations. We further verify the scalability of the proposed routing schemes in a larger network.

Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip

Optical network-on-chip (ONoC) architecture offers ultrahigh bandwidth, low latency, and low power dissipation for new-generation manycore systems. However, the benefits in communication performance and energy efficiency will be diminished by communication contention. The intrinsic thermal susceptibility is another challenge for ONoC designs. Under on-chip temperature variations, core functional devices suffer from significant thermal-induced optical power loss, which seriously threatens ONoCs’ reliability. In this article, we develop novel routing techniques to resolve both issues for ONoCs. By analyzing the thermal effect in ONoCs, we first present a routing criterion at the network level. Combined with device-level thermal tuning, it can implement thermal-reliable ONoCs. Two routing approaches, including a mixed-integer linear programming (MILP) model and a heuristic algorithm (called CAR), are further proposed to minimize communication conflicts based on guaranteed thermal reliability, and meanwhile, maximize the communication energy efficiency in the presence of on-chip thermal variations. By applying the criterion, our approaches achieve excellent performance with largely reduced complexity of design space exploration. The evaluation results based on both synthetic traffic patterns and realistic benchmarks validate the effectiveness of our approaches with an average of 126.95% improvement in communication performance and 16.12% reduction in energy overhead compared to state-of-the-art techniques. CAR only introduces 7.20% performance difference compared to the MILP model and is more scalable to large-size ONoCs.

A Table-Free Approximate Q-Learning-Based Thermal-Aware Adaptive Routing for Optical NoCs

Optical networks-on-chips (NoCs) based on silicon photonics have been proposed as an emerging communication architecture for many-core chip multiprocessors. However, the thermal sensitivity of silicon photonics is one of the major challenges. $Q$ -learning-based adaptive routing has been proposed in related work to mitigate the thermal issue. However, table overhead of the traditional table-based $Q$ -routing would scale up quickly with the increase of network size. In this article, we propose a table-free approximate $Q$ -learning-based thermal-aware adaptive routing to find optimal low-loss paths in the presence of on-chip temperature variations. The simulation results show that the proposed table-free approximate $Q$ -learning-based adaptive routing can converge faster and it can achieve similar optimization effect as compared to the best optimization effect of the traditional table-based $Q$ -routing. The performance gap between the proposed approximation method and the traditional table-based $Q$ -routing expands when the network size increases.

A thermal-sensitive design of a 3D torus-based optical NoC architecture

In order to overcome limitations of traditional electronic interconnects in terms of power efficiency and bandwidth density, optical networks-on-chip (NoC) based on silicon photonics have been proposed as an emerging on-chip communication architecture for chip multiprocessors (CMPs) with large core counts. However, due to thermo-optic effects, wavelength-selective silicon photonic devices such as microresonators suffer from temperature-dependent wavelength shift. In this work, we propose a thermal-sensitive design of a 3D torus-based optical NoC architecture. For the 3D torus-based optical NoC architecture, we propose a hybrid optical-electronic router architecture with a fully-connected 7 × 7 optical switching fabric. Besides, a thermal-sensitive routing algorithm is proposed to optimize the optical power loss in the presence of on-chip temperature variations. Simulation results show that for a set of synthetic traffic patterns, the proposed 3D torus-based optical NoC with the thermal-sensitive routing reduces the average thermal-induced optical power loss by 14.3% and 17% respectively as compared to the matched 3D torus-based optical NoC and the 3D mesh-based optical NoC with the traditional XYZ routing. For a set of real applications, the proposed 3D torus-based optical NoC with the thermal-sensitive routing reduces the worst-case optical power loss by 7.9% and 14.6% respectively as compared to the matched 3D torus-based optical NoC and the 3D mesh-based optical NoC with the traditional XYZ routing.

An Insight Into Self-Heating Effects and Its Implications on Hot Carrier Degradation for Silicon-Nanotube-Based Double Gate-All-Around (DGAA) MOSFETs

Silicon-Nanotube-based ultra-thin DGAA MOSFETs have been extensively studied for their superior immunity to short channel effects (SCEs) and better drive current capability; however, the reliability issues owing to self-heating effects (SHEs) and hot carrier injection (HCI) degradation are yet to be investigated systematically. In advanced non-planar device structures, an increase in power density due to ultra-scaled device dimensions can aggravate both the carrier heating as well as lattice heating. In this paper, 3-dimensional (3-D) electrothermal (ET) simulations using coupled hydrodynamic and thermodynamic transport models are performed to analyze the electrothermal behavior and SHEs in ultra-thin DGAA MOSFET. 3-D TCAD simulation parameters are calibrated with the data obtained from the literature. Through advanced 3-D ET simulations, we demonstrate that the device thermal contact resistance adversely influences both the carrier temperature as well as lattice temperature. The implication of SHE on the device output drive current reduction is also analyzed. The effective drive current method is used to observe the impact of SHE on the intrinsic delay of the device. Further, the performance of the device due to HCI is also highlighted. HCI significantly degrades the overall device performance leading to increased gate leakage current. Finally, the reliability issues induced by SHEs with on-chip ambient temperature variations have also been interpreted using Sentauras based TCAD simulator.

LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip

Silicon nanophotonics technology is being considered for future networks-on-chip (NoCs) as it can enable high bandwidth density and lower latency with traversal of data at the speed of light. But, the operation of photonic NoCs (PNoCs) is very sensitive to on-chip temperature and process variations. These variations can create significant reliability issues for PNoCs. For example, a microring resonator (MR) may resonate at another wavelength instead of its designated wavelength due to thermal and/or process variations, which can lead to bandwidth wastage and data corruption in PNoCs. This paper proposes a novel run-time framework called LIBRA to overcome temperature- and process variation- induced reliability issues in PNoCs. The framework consists of (i) a device-level reactive MR assignment mechanism that dynamically assigns a group of MRs to reliably modulate/receive data in a waveguide based on the chip thermal and process variation characteristics; and (ii) a system-level proactive thread migration technique to avoid on-chip thermal threshold violations and reduce MR tuning/ trimming power by dynamically migrating threads between cores. Our simulation results indicate that LIBRA can reliably satisfy on-chip thermal thresholds and maintain high network bandwidth while reducing total power by up to 61.3 percent, and thermal tuning/trimming power by up to 76.2 percent over state-of-the-art thermal and process variation aware solutions.

Real-time compensation of errors in refractive index shift measurements of microring sensors using thermo-optic coefficients.

We report a method for compensation of errors caused by temperature fluctuations in refractive index measurements using Silicon photonic microring sensors. The method involves determination of resonance wavelength shifts caused by thermal fluctuations using real-time measurement of on-chip temperature variations and thermo-optic coefficient (TOC) of analyte liquids. Resistive metal lines patterned around Silicon microrings are used to track temperature variations and TOC of analyte is calculated by measuring wavelength shifts caused by controlled increments in device temperature. The TOC of de-ionized water is determined to be -1.12 × 10-4/°C, with an accuracy of ±8.26 × 10-6/°C. In our system, chip-surface temperature variations were measured with an instrument limited precision of 0.004 °C yielding a factor of 16 enhancement in tracking accuracy compared to conventional, bottom-of-chip temperature measurement. We show that refractive index detection limit of the microring sensor is also improved by the same factor.

A Learning-Based Thermal-Sensitive Power Optimization Approach for Optical NoCs

Optical networks-on-chip (NoCs) based on silicon photonics have been proposed as emerging on-chip communication architectures for chip multiprocessors with large core counts. However, due to the thermal sensitivity of optical devices used in optical NoCs, on-chip temperature variations cause significant thermal-induced optical power loss, which would counteract the power advantages of optical NoCs. To tackle this problem, in this work, we propose a learning-based thermal-sensitive power optimization approach for mesh- or torus-based optical NoCs in the presence of temperature variations. The key techniques proposed include an initial device-setting and thermal-tuning mechanism that is a device-level optimization technique, and a learning-based thermal-sensitive adaptive routing algorithm that is a network-level optimization technique. Simulation results of an 8x8 mesh-based optical NoC show that the proposed initial device-setting and thermal-tuning mechanism confines the worst-case thermal-induced optical energy consumption to be on the order of tens of pJ/bit, by avoiding significant thermal-induced optical power loss caused by temperature-dependent wavelength shifts. Besides, it shows that the learning-based thermal-sensitive adaptive routing algorithm is able to find an optimal path with the minimum estimated thermal-induced optical power consumption for each communication pair. The proposed routing has a greater space for optimization, especially for applications with more long-distance traffic.

Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability

Increasing the accuracy of circuit delay estimation using Non Linear Delay Model (NLDM) in nanometer range CMOS technologies is highly challenging. To solve this issue, people have started using effective current source model (ECSM) and composite current source model (CCSM), which can both be derived from each other. For a standard cell, ECSM stores certain predefined threshold crossing points (TCPs) of the output voltage waveform with respect to several input transition time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</sub> ) and load capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">l</sub> ) values. In this work, we propose an analytical timing model relating all TCPs with Cl and TR values for inverter standard cell. We derive the relationship between the cell size and the model coefficients. We also derive the region of validity of the model in (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</sub> , C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">l</sub> ) space and determine its relationship with cell size. The proposed model is in good agreement with HSPICE simulations with a maximum error of 2.5%. We use this model and the derived relationships with cell size to reduce the number of simulations in ECSM library characterization. Due to process, voltage and on-chip temperature (PVT) variation, re-characterization is done at several PVT corners. In addition, layout dependent effects also lead to an unexpected variation in cell performance. To reduce the characterization effort, we derive relationships of variation of our model coefficients and regions of validity with cell size in mechanical stress enabled CMOS technologies, considering cell layout parameters. We also derive relationships of our model's coefficients with on-chip supply voltage and temperature variations. We use these relationships in reducing number of HSPICE simulations in ECSM re-characterization significantly.

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip

Multiprocessor systems-on-chip show a trend toward integration of tens and hundreds of processor cores on a single chip. With the development of silicon photonics for short-haul optical communication, wavelength division multiplexing (WDM)-based optical networks-on-chip (ONoCs) are emerging on-chip communication architectures that can potentially offer high bandwidth and power efficiency. Thermal sensitivity of photonic devices is one of the main concerns about the on-chip optical interconnects. We systematically modeled thermal effects in optical links in WDM-based ONoCs. Based on the proposed thermal models, we developed OTemp, an optical thermal effect modeling platform for optical links in both WDM-based ONoCs and single-wavelength ONoCs. OTemp can be used to simulate the power consumption as well as optical power loss for optical links under temperature variations. We use case studies to quantitatively analyze the worst-case power consumption for one wavelength in an eight-wavelength WDM-based optical link under different configurations of low-temperature-dependence techniques. Results show that the worst-case power consumption increases dramatically with on-chip temperature variations. Thermal-based adjustment and optimal device settings can help reduce power consumption under temperature variations. Assume that off-chip vertical-cavity surface-emitting lasers are used as the laser source with WDM channel spacing of 1 nm, if we use thermal-based adjustment with guard rings for channel remapping, the worst-case total power consumption is 6.7 pJ/bit under the maximum temperature variation of 60 °C; larger channel spacing would result in a larger worst-case power consumption in this case. If we use thermal-based adjustment without channel remapping, the worst-case total power consumption is around 9.8 pJ/bit under the maximum temperature variation of 60 °C; in this case, the worst-case power consumption would benefit from a larger channel spacing.

Towards Adaptively Tuned Silicon Microring Resonators for Optical Networks-on-Chip Applications

We propose to monitor the spectral alignment of silicon microring resonators with an optical carrier in the 1300 / 1550 nm wavelengths by photodetecting the microring internal power using a defect-state-absorption-based silicon photodetector integrated along the microring. We can thereby adaptively tune the resonance wavelength based on the photocurrent to compensate the spectral misalignment using either an integrated electro-optical or thermo-optical tuner. Our analysis suggests that the spectral alignment can be preserved within ~±0.01 nm upon an on-chip temperature variation of 10°C or a carrier wavelength drift of ±60 pm, assuming a closed-loop operation time shorter than 900 μs and a total power consumption of ~0.65 mW for 1550 nm and ~1.1 mW for 1300 nm. As a proof-of-concept, we experimentally demonstrate monitoring the spectral alignment using the photocurrents from a silicon microring carrier-injection switch upon a 10 Gb/s data transmission in 1550 nm, while subjecting the switch to a temperature variation between 20 - 33 °C. We further analyze the feasibility of integrating such an adaptively tuned silicon microring resonator into a single-channel M-input N-output (M × N) optical switch-matrix. Our worst-case analysis suggests that a 16 × 16 switch-matrix in an estimated total footprint of ~640 μm × 480 μm imposes an estimated total power consumption of ~167 mW for 1550 nm, and a 13 × 13 switch-matrix in an estimated total footprint of ~520 μm × 390 μm imposes an estimated power consumption of ~185 mW for 1300 nm.

Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization

With the continuing scaling of CMOS technology, on-chip temperature and thermal-induced variations have become a major design concern. To effectively limit the high temperature in a chip equipped with a cost-effective cooling system, thermal specific approaches, besides low power techniques, are necessary at the chip design level. The high temperature in hotspots and large thermal gradients are caused by the high local power density and the nonuniform power dissipation across the chip. With the objective of reducing power density in hotspots, we propose two placement techniques that spread cells in hotspots over a larger area. Increasing the area occupied by the hotspot directly reduces its power density, leading to a reduction in peak temperature and thermal gradient. To minimize the introduced overhead in delay and dynamic power, we maintain the relative positions of the coupling cells in the new layout. We compare the proposed methods in terms of temperature reduction, timing, and area overhead to the baseline method, which enlarges the circuit area uniformly. The experimental results showed that our methods achieve a larger reduction in both peak temperature and thermal gradient than the baseline method. The baseline method, although reducing peak temperature in most cases, has little impact on thermal gradient.

High-throughput, energy-efficient network-on-chip-based hardware accelerators

Several emerging application domains in scientific computing demand high computation throughputs to achieve terascale or higher performance. Dedicated centers hosting scientific computing tools on a few high-end servers could rely on hardware accelerator co-processors that contain multiple lightweight custom cores interconnected through an on-chip network. With increasing workloads, these many-core platforms need to deliver high overall computation throughput while also being energy-efficient. Conventional multicore architectures can achieve a limited computational throughput due to the inherent multi-hop nature of the on-chip network infrastructure. By inserting long-range links that act as shortcuts in a regular network-on-chip (NoC) architecture, both the achievable bandwidth and energy efficiency of a multicore platform can be significantly enhanced. In this paper, we first propose a NoC-driven use-case model for throughput-oriented scientific applications, and subsequently use the model to study the effect of using long-range links in conjunction with different resource allocation strategies on reducing the overall on-chip communication and enhancing computational throughput. NoCs with both wired and on-chip wireless links are explored in the study. We also evaluate our NoC-based platforms with respect to energy-efficiency and power consumption. We analyze how throughput and power consumption are correlated with the statistical properties of the application traffic. In addition, we compare and analyze chip-level thermal profiles for these alternatives. Our experiments using kernels from a popular phylogenetic inference application suite show that we can deliver computation throughput over 1011 operations per second, consuming ∼0.5nJ per operation, while ensuring that on-chip temperature variation is within 26°C.

Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs

Chip heating and nonuniform distribution of hot and cool zones on the die negatively affect reliability and robustness to failures of nanometer integrated circuits. In fact, signal propagation on interconnects slows down as temperature rises; for long wires crossing regions at different temperatures, such as the clock network, thermally induced delay and skew get altered and may result in timing faults. Failures of this kind are difficult to face due to their transient nature. This paper focuses on clock tree design for the class of embedded systems-on-chip with spatially nonuniform but temporally stationary thermal profiles. We contribute two algorithms for the thermal-aware clock network design that take into account on-chip temperature variations of this nature. The experimental results that we have collected on a number of examples and for different thermal profiles show that, in the presence of on-chip spatial temperature gradients, clock trees designed using a standard methodology incur very significant skew violations, thus originating circuit failures. Instead, clock networks designed using the algorithms presented in this paper always satisfy the initial skew bound.

Quantified Temperature Effect in a CMOS Image Sensor

In recent years, CMOS image sensors (CISs) have increasingly become major players in the solid-state imaging market, a market in which charge-coupled device image sensors were once the dominant product. Exceptional circuit integration capability makes CMOS imagers suitable for implementation in a single-chip imaging system while inducing the temperature variation of an image sensor. In this paper, global and local high-leakage nonuniformities induced by on-chip temperature variations were controlled by both a Peltier junction device and on-chip resistors. Two test chips were fabricated using TSMC 0.13-?m CIS processes and TSMC 1-poly 6-metal 0.18-?m process technology, respectively. As expected, fixed-pattern noise increased with temperature. To quantify the influence of temperature, the maximum depth of an affected region was defined as DAR. The experimental results revealed that the DAR index increased with either an increase in power consumption or a space reduction between the resistor and the pixel array. The DAR index not only characterized affected regions in the experiment but also provided a valuable reference regarding temperature protection for future imager designs.

Energy Awareness and Uncertainty in Microarchitecture-Level Design

The authors present microarchitecture-level statistical models for characterizing process and system parameter variability, concentrating on gate length and on-chip temperature variations. To assess the effect of microarchitecture decisions on these variations, and vice versa, they propose a joint performance, power, and variability metric that distinguishes among various design choices.