On-chip Signaling Research Articles

Integrated phase-change photonic devices and systems

Abstract

High-Speed On-Chip Signaling: Voltage or Current-Mode?

In this paper, we investigate several on-chip signaling schemes. Specifically, we compare different voltage-mode (VM) and current-mode (CM) signaling schemes considering power, performance, and robustness. In addition, we propose a new CM signaling scheme that uses a simple NAND-NOR gate transmitter circuit and a current-comparator-based receiver circuit. We implemented each signaling scheme using a 45 nm CMOS technology. The extracted simulation results show that a traditional CM signaling scheme consumes 58–78% less power compared to a traditional buffered VM signaling scheme in the 1–3 GHz frequency range. Our proposed CM signaling scheme consumes up to 95% and 81% lower power compared to buffered VM and existing CM schemes, respectively. In addition, the proposed CM signaling scheme has 37–41% lower latency with similar slew-rates compared to the buffered signaling scheme.

A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM

This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.

Integrated photonics for on-chip signaling

Integrated photonics for on-chip signaling

A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination

A switched-diode termination (SDT) is proposed to implement a low-power transceiver circuit for on-chip single-ended signaling through a through-silicon via (TSV). The channel signal swing is limited to 40 mV by the SDT to reduce the transmitter (TX) power. An inverter-cascade amplifier is used to reduce the receiver (RX) power. The SDT consists of an nMOS diode and a pMOS diode, which are connected in a series between power rails through the RX input node. Only one of these two diodes is switched on depending on the RX output data, which eliminates the short-circuit current of the center-tap resistor termination. Inverter feedback is applied to the cascade amplifier of the RX to increase the bandwidth from 0.9 to 5.0 GHz. The transceiver in the 65-nm CMOS process combined with an emulated five-stack TSV on the same chip works at 8 Gb/s with 149 fJ/b/pF and a 1.2-V supply.

Robust On-chip Signaling by Staggered and Twisted Bundle

Robust On-chip Signaling by Staggered and Twisted Bundle

A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS

In this paper, a crosstalk compensation scheme for high speed single-ended on-chip signaling is presented. To reduce the effect of crosstalk in bandwidth enhanced channel employing capacitively driven interconnect, a crosstalk feed-forward equalizer is proposed, which compensates for the low-pass nature of the crosstalk. The proposed scheme is verified using a three-channel 10 mm on-chip interconnect implemented in 130 nm CMOS process. Measurement results show that the proposed transceiver effectively removes the crosstalk for data rates of up to 2.5-Gb/s while consuming 0.96 mW, which corresponds to energy efficiency of 0.41 pJ/bit.

Tailoring of dispersion and nonlinear properties of integrated silicon waveguides for signal processing applications

Integrated silicon waveguides serve as a transmission medium for on-chip signaling, and they are also used to form various types of devices for communication and signal processing applications. In this paper, we present some recent progress in tailoring the physical properties of the silicon waveguides such as chromatic dispersion and nonlinearity. Using slot structures, both dispersion and nonlinearity can be tailored by more than an order of magnitude, which is a very useful feature in many signal processing applications.

Robust On-Chip Signaling by Staggered and Twisted Bundle

Existing shield insertion for multiple signal nets can lead to a nonuniformly distributed, capacitive-coupling length and inductive return paths, introducing large delays and delay variation by crosstalk. This article discusses a twisted, staggered interconnect structure that reduces both inductive and capacitive crosstalk. The proposed design reduces delay by 25% and reduces delay variation by 25times compared to designs employing coplanar shields.

A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines

A 9-Gbit/s serial link transceiver for on-chip global signaling, and techniques for the design of on-chip transmission lines, are presented. In a prototype device, a transmitter serializes 8-b 1.125-Gbyte/s parallel data and transmits serial data over a 5.8-mm lossy on-chip transmission line. A receiver de-serializes the received data with the help of a digitally tuned interpolator. An on-chip lossy transmission line scheme is described. In the prototype, self-test circuitry verifies the recovered, de-serialized data against the original data and counts the number of discrepancies. The prototype transceiver, implemented in 0.13-mum 8-metal CMOS, achieves 9 Gbit/s with pre-defined data patterns.

Differential current-mode sensing for efficient on-chip global signaling

We present a new on-chip signaling method that relies on differential current-mode sensing to improve both delay and energy dissipation compared to conventional inverter repeaters. The proposed method can be used for point-to-point as well as N-to-1 connections. Several experimental point-to-point transceivers with different interconnect length and an inverter repeater-based interconnect were implemented in 0.11 /spl mu/m, 1.2V CMOS. Hardware measurements indicate that the proposed current-sensed transceiver produces 65% of the delay/mm of a repeater-based transceiver while dissipating 51% of its average switching energy/mm for a 10 mm interconnect. An additional 10% energy reduction relative to the inverter-repeater transceiver is possible if shorter current pulses are transmitted through the interconnect.

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.

Global interconnect design in a three-dimensional system-on-a-chip

A stochastic model for the global net-length distribution of a three-dimensional system-on-a-chip (3D-SoC) is derived. Using the results of this model, a global interconnect design window for a 3D-SoC is established by evaluating the constraints of: 1) wiring area; 2) clock wiring bandwidth; and 3) crosstalk noise. This window elucidates the optimum 3D-SoC global interconnect parameters for minimum pitch, minimum aspect ratio, and maximum clock frequency. In comparison to a two-dimensional system-on-a-chip (2D-SoC), the design window expands for a 3D-SoC to allow greater flexibility of interconnect parameters, thus increasing the guardbands to process variations. In addition, the limit on the maximum global clock frequency is revealed to increase as S/sup 2/, where S is the number of strata. This increase in on-chip signaling rate, however, comes at the expense of I/O density, highlighting the need for new high-density-I/O packaging techniques to exploit the full potential of 3D-SoC.

Current mode, low-power, on-chip signaling in deep-submicron CMOS technology

This paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The technique uses multilevel, current-mode signaling as its core. The number of levels is determined by estimating the bandwidth of the wire. A closed-form expression has been presented here describing the bandwidth of a wire modeled as a first-order RLC circuit. An algorithm is presented for computing the levels of the current given target bit rate, bit-error rate, and wire characteristics. Simulation results using HSPICE from Avant! show that the algorithm for computing the wire bandwidth presented here has an average error of less than 10%. Experimental results on a set of benchmark signaling problems implemented in a 0.25-/spl mu/m 2.5-V CMOS process, show that using four levels of current instead of the standard two levels allows a two-fold reduction in the power and a reduction of 1.4 times the area.

Low-swing on-chip signaling techniques: effectiveness and robustness

This paper reviews a number of low-swing on-chip interconnect schemes and presents a thorough analysis of their effectiveness and limitations, especially on energy efficiency and signal integrity. In addition, several new interface circuits presenting even more energy savings and better reliability are proposed. Some of these circuits not only reduce the interconnect swing, but also use very low supply voltages so as to obtain quadratic energy savings. The performance of each of the presented circuits is thoroughly examined using simulation on a benchmark interconnect circuit. Significant energy savings up to a factor of six have been observed.

Codec has on-chip signaling for phone applications : Walt Heinzer and Steve Bolger. Electronics p. 134 (7 June 1979)

Codec has on-chip signaling for phone applications : Walt Heinzer and Steve Bolger. Electronics p. 134 (7 June 1979)