On-chip Resistors Research Articles

An in-situ thermoelectric measurement apparatus inside a thermal-evaporator

At the ultra-thin limit below 20 nm, a film’s electrical conductivity, thermal conductivity, or thermoelectricity depends heavily on its thickness. In most studies, each sample is fabricated one at a time, potentially leading to considerable uncertainty in later characterizations. We design and build an in-situ apparatus to measure thermoelectricity during their deposition inside a thermal evaporator. A temperature difference of up to 2 K is generated by a current passing through an on-chip resistor patterned using photolithography. The Seebeck voltage is measured on a Hall bar structure of a film deposited through a shadow mask. The measurement system is calibrated carefully before loading into the thermal evaporator. This in-situ thermoelectricity measurement system has been thoroughly tested on various materials, including Bi, Te, and Bi2Te3, at high temperatures up to 500 K. Working reliably and precisely, the in-situ measurement system would help to study physics during film growth or speedup our search for better thermoelectric materials.

Improved Q-Factor 3D Double-Layered On-Chip Resistor with Shielded Ground Conductor

In this paper, a double-layered structure to form an N-Well meander-line structure by added shielding grounded conductor to improve the quality factor on-chip resistors in high frequency operation is presented. An additionally added shielding ground conductor is applied to the proposed structure to reduce the induced capacitance coupling. and substrate losses for further improvement of the Q factor were also presented. Sonnet EM simulation result validated that double-layered structure via the shielding ground conductor was effective to improve their quality factors by 37.8% from 1.209 to –0.752 and reducing capacitance coupling effect by 57.92% from 55.23fF to 23.24fF during operating frequency at 10 GHz compared with conventional N-Well meander-line resistors. A novel structure in the design of a double-layered on-chip resistor with a shielding grounded conductor showed that capacitance coupling of parasitic effect was reduced; therefore, a low Q factor in high-frequency operations was obtained.

Cryogenic NbTiN thin film resistors fabricated by using reactive magnetron sputtering

Reactive magnetron sputtering has been applied for fabrication of NbTiN thin film resistors operating at liquid helium temperature. The resistivity of the NbTiN films at 4 K can be tuned in a wide range from about 100 μΩ cm to 10,000 μΩ cm with sputtering parameters such as discharge current and sputtering pressure. This broad tuning range greatly facilitates the design and fabrication of on-chip lumped-element resistors for millimeter and submillimeter integrated circuits. The NbTiN thin film resistors are found to be nitrogen-deficient, and the resistivity is strongly dependent on the nitrogen atomic ratio. A numerical model of reactive magnetron discharge has been utilized to understand the tuning mechanism, and the simulation results are in qualitative agreement with the measured ones.

Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator

A tiny-size ultra-low voltage CMOS voltage reference operating at quiescent picoamp scale has been proposed in this paper to fit the high standards of modern wireless microsystems. Without any on-chip resistor or operational amplifier (opamp), the sensitive core of the proposed voltage reference is protected from the glitches of the power supply via a temperature-dependent cascode current source biased by the output. The upper limit of the output temperature range is broadened by the increased diode leakage current of the proposed current generator. The case study deals with implementation of the new circuit and post-layout simulation results in 0.18-μm CMOS technology. The circuit occupies an active area of 629 μm2, consuming almost 690 pA from 0.3 V minimum supply voltage at room temperature. The untrimmed 229 mV output voltage exhibits an average temperature coefficient (TC) of 47.39 ppm/°C over the −40 °C–140 °C temperature range. The line-voltage sensitivity (LS) is 0.17%/V when the input supply is varied from 0.3 V to 1.8 V, and can be improved by 9 × if the lower limit of the power supply is increased to 0.4 V. The DC power supply ripple rejection (PSRR) is lower than −80 dB for the line voltage beyond 0.5 V.

Capacitively-Loaded Thin-Film Lithium Niobate Modulator With Ultra-Flat Frequency Response

Traveling-wave electro-optic (E-O) modulators based on thin-film lithium niobate (TFLN) have attracted much attention recently, as low half-wave voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\pi }$ </tex-math></inline-formula> ) and wide modulation bandwidth can be realized with a small footprint. A flat E-O response of the modulator relies on low microwave loss, perfect velocity match and suitable terminal resistance. In this Letter, we present velocity-matched TFLN modulator based on low-loss capacitively-loaded traveling-wave electrodes (CL-TWEs) with an on-chip terminal resistor. The effect of termination resistance on the E-O frequency response is theoretically analyzed and experimentally confirmed. The TFLN modulator with 6-mm modulation length exhibit a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\pi }$ </tex-math></inline-formula> of 2.7 V and a 6.4-dB electrical bandwidth over 160 GHz. By adopting a termination resistance slightly lower than the characteristic impedance of the CL-TWEs, an ultra-flat E-O response has been demonstrated with fluctuation less than 1-dB up to 50 GHz, consistent with the theoretical prediction.

A 16 MHz CMOS RC Frequency Reference With ±90 ppm Inaccuracy From −45 °C to 85 °C

This article presents a 16-MHz <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> frequency reference implemented in a standard 180-nm CMOS process. It consists of a frequency-locked loop (FLL) in which the output frequency of a digitally controlled oscillator (DCO) is locked to the frequency-phase characteristic of a Wien bridge <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> filter. Since it is made from on-chip resistors and capacitors, the filter’s characteristic is temperature dependent. To compensate for this, the control signal of the DCO is derived by digitizing the filter’s output phase and combining it with the digital output of a Wheatstone bridge temperature sensor. After a two-point trim, this digital temperature compensation scheme achieves an inaccuracy of ±90 ppm from −45 °C to 85 °C. The frequency reference draws 220 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> from a 1.8-V supply, with a supply sensitivity of 0.12%/V and a 320-ppb Allan Deviation floor for a 10-s stride.

A Constant gₘ Current Reference Generator With Pseudo Resistor-Based Compensation

Most analog circuits need a current reference generator to provide a stable biasing point for the transistors. Given the limited voltage headroom in advanced node technologies, there would be notable restrictions on the tolerance of the reference current deviation. Use of off-chip reference generators adds to the size of the system while the on-chip reference current generators are still partially dependent on the on-chip resistor values which is prone to technology variations. We propose an on-chip reference generator with a fully off-chip resistor which has less sensitivity to process variations. Monte-Carlo simulation results shows that the proposed has 31% more precision compared to the conventional on-chip reference generator. Measurement results in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~{{\mu }}\text{m}$ </tex-math></inline-formula> CMOS shows that the chip produces a stable reference current that is defined based on an off-chip resistor. The proposed structure consumes the same current as conventional and does not add to the power consumption.

Analog Frontend for Reliable Human Body Temperature Measurement for IoT Devices

In this paper an analog frontend for a reliable measurement of the human body temperature is presented. A new and novel temperature calibration technique using an on-chip resistor was developed specifically for the analog frontend. The discussed analog frontend consists of a bandgap current reference, a precision current source, a programmable gain amplifier, a voltage source proportional to absolute temperature and an on-chip calibration resistor. The developed calibration technique enables very high accuracy, even 0.1 °C, to be obtained in a very wide temperature range. This calibration method was elaborated for integrated circuits operating in temperatures from −40 °C to +125 °C. The presented analog frontend consumes no more than 185 μA and was designed and manufactured with United Microelectronics Corporation (UMC) CMOS 130 nm technology. The data presented in the paper were obtained from process corner and Monte Carlo simulations as well as from measurements. The measurements were taken using a manual wafer prober with climate-controlled microchamber, at temperatures ranging from −40 °C to +125 °C.

Optimization of On-Chip Meander Line Resistor by Using DOE Method

A new analysis method for the improvement and optimization of the geometrical layout parameters associated with the on-chip n-well meander line resistor layout to have a low-quality factor (Q) and better performance operating at high frequency is investigated through factorial design experiment DOE efficient method. The factors influencing the Q-factor include the width, line length, line segment, and spacing were studied. The factorial design DOE process model was formulated using the Minitab statistical package. The result in terms of the quality factor and resistance for comparison between the proposed optimized design and conventional design layout is simulated by Sonnet electromagnetic simulation tool and validated by the theoretical mathematical prediction calculation based on an equation of lumped physical model had been presented. Results indicate that a shorter line length and line segment lead to a high impact on the improvement of the Q-factor. By the factorial design experiment, the optimized structure with a single line segment, the width of 5 µm, spacing of 1 µm, and line length of 16 µm had been established to have a lower Q-factor compared to the conventional configuration. The Q-factor was improved by 93% from 1.193 to 0.071 at the targeted 1 GHz frequency by the Sonnet EM simulation tool. The simulation result had shown comparative agreement to the theoretical mathematical predictions analysis result.

A self-contained acoustofluidic platform for biomarker detection.

Self-contained microfluidic platforms with on-chip integration of flow control units, microreactors, (bio)sensors, etc. are ideal systems for point-of-care (POC) testing. However, current approaches such as micropumps and microvalves, increase the cost and the control system, and it is rather difficult to integrate into a single chip. Herein, we demonstrated a versatile acoustofluidic platform actuated by a Lamb wave resonator (LWR) array, in which pumping, mixing, fluidic switching, and particle trapping are all achieved on a single chip. The high-speed microscale acoustic streaming triggered by the LWR in the confined microchannel can be utilized to realize a flow resistor and switch. Variable unidirectional pumping was realized by regulating the relative position of the LWR in various custom-designed microfluidic structures and adoption of different geometric parameters for the microchannel. In addition, to realize quantitative biomarker detection, the on-chip flow resistor, micropump, micromixer and particle trapper were also integrated with a CMOS photo sensor and electronic driver circuit, resulting in an automated handheld microfluidic system with no moving parts. Finally, the acoustofluidic platform was tested for prostate-specific antigen (PSA) sensing, which demonstrates the biocompatibility and applied potency of this proposed self-contained system in POC biomedical applications.

A 15 Gbps-NRZ, 30 Gbps-PAM4, 120 mA laser diode driver implemented in 0.15-µm GaAs E-mode pHEMT technology

This paper presents the design and testing of a 15 Gbps non-return-to-zero (NRZ), 30 Gbps 4-level pulse amplitude modulation (PAM4) configurable laser diode driver (LDD) implemented in 0.15-µm GaAs E-mode pHEMT technology. The driver bandwidth is enhanced by utilizing cross-coupled neutralization capacitors across the output stage. The output transmission-line back-termination, which absorbs signal reflections from the imperfectly matched load, is performed passively with on-chip 50-Ω resistors. The proposed 30 Gbps PAM4 LDD is implemented by combining two 15 Gbps-NRZ LDDs, as the high and low amplification paths, to generate PAM4 output current signal with levels of 0, 40, 80, and 120 mA when driving 25-Ω lasers. The high and low amplification paths can be used separately or simultaneously as a 15 Gbps-NRZ LDD. The measurement results show clear output eye diagrams at speeds of up to 15 and 30 Gbps for the NRZ and PAM4 drivers, respectively. At a maximum output current of 120 mA, the driver consumes 1.228 W from a single supply voltage of –5.2 V. The proposed driver shows a high current driving capability with a better output power to power dissipation ratio, which makes it suitable for driving high current distributed feedback (DFB) lasers. The chip occupies a total area of 0.7 × 1.3 mm2.

All–MOS self-powered subthreshold voltage reference with enhanced line regulation

A nano-watt self-powered voltage reference configuration has been developed for the integrated microsystems in standard CMOS technology. The circuit is highly immune to temperature variations, and can be made very insensitive to the power supply glitches originating from the simple regulation mechanisms used to harvest energy from the environment. The proposed reference is an all-MOS topology without operational amplifier or on-chip resistors, generating a stable output with excellent line regulation owing to the modifications proposed to suppress the line voltage variations. All the MOS devices are working in weak inversion to ensure operation at nano-ampere current levels. Simulated in 0.18-µm standard CMOS process, a prototype of the proposed reference consumes an overall power of 14 nW at 0.7 V minimum supply. The average voltage reference is 255 mV with an average temperature coefficient of 17.05 ppm/°C across −40 °C to +125 °C. The line regulation is 0.00797%/V and 0.00456%/V, respectively, when the reference is subjected to a line voltage of 0.9–2.0 V and 1.0–2.0 V. The power supply rejection ratio is −110 dB, −91 dB and −68 dB for 0.1 Hz, 10 Hz, and 1 MHz at room temperature, respectively.

A Low-Power Relaxation Oscillator With Switched-Capacitor Frequency-Locked Loop for Wireless Sensor Node Applications

This letter presents a 600-kHz relaxation oscillator with 2.2- $\mu \text{W}$ power consumption. A low-power frequency-locked loop (FLL) structure is proposed to increase the frequency immunity against process, voltage, and temperature variations. A front regulator is proposed to further enhance the voltage stability and widen the voltage range. A current-injection scheme is proposed to compensate the frequency shift due to the temperature shift of the on-chip resistor. Fabricated with 180-nm technology, this oscillator can operate at an unregulated supply from 1.1 to 3.3 V with 0.046%/V voltage stability. The measured temperature stability is 48.69 ppm/°C from −45 °C to 125 °C and the measured jitterrms is 1.56 ns with 120-k hits.

A 1.8 V 18.13 MHz Inverter-Based On-Chip RC Oscillator with Flicker Noise Suppression Using Logic Transition Voltage Feedback

An inverter-based on-chip resistor capacitor (RC) oscillator with logic transition voltage (LTV) tracking feedback for circuit delay compensation is presented. In order to achieve good frequency stability, the proposed technique considers the entire inverter chain as a comparator block and changes the LTV to control the oscillation frequency. Furthermore, the negative feedback structure also reduces low-frequency offset phase noise. With a 1.8 V supply and at room temperature, the suggested oscillator operates at 18.13 MHz, consuming 245.7 μ W. Compared to the free-running case, the proposed technique reduces phase noise by 7.7 dB and 5.45 dB at 100 Hz and 1 kHz, respectively. The measured phase noise values are −60.09 dBc/Hz at 1 kHz with a figure of merit (FOM) of 151.35 dB/Hz, and −106.27 dBc/Hz at 100 KHz with an FOM of 157.53 dBc/Hz. The proposed oscillator occupies 0.056 mm2 in a standard 0.18 μ m CMOS process.

A ±4-A High-Side Current Sensor With 0.9% Gain Error From −40 °C to 85 °C Using an Analog Temperature Compensation Technique

This paper presents a fully integrated shunt-based current sensor that supports a 25-V input common-mode range while operating from a single 1.5-V supply. It uses a high-voltage beyond-the-rails ADC to directly digitize the voltage across an on-chip shunt resistor. To compensate for the shunt’s large temperature coefficient of resistance (~0.335%/°C), the ADC employs a proportional-to-absolute-temperature voltage reference. This analog compensation scheme obviates the need for the explicit temperature sensor and calibration logic required by digital compensation schemes. The sensor achieves 1.5-V noise over a 2-ms conversion time while drawing only 10.9 $\mu \text{A}$ from a 1.5-V supply. Over a ±4-A range, and after a one-point trim, the sensor exhibits a 0.9% (maximum) gain error from −40 °C to 85 °C and a 0.05% gain error at room temperature.

Process compensated bipolar junction transistor‐based CMOS temperature sensor with a ±1.5°C (3σ) batch‐to‐batch inaccuracy

A bipolar junction transistor (BJT)-based CMOS temperature sensor exploiting the piecewise BJT process spread compensation property of the base recombination current is proposed to reduce the process variations of the base-emitter voltage ( V be ). The weighted combinations of different on-chip resistors are explored to minimise their associated process spread. Fabricated in standard 0.18-μm CMOS, the chip prototype occupies an active area of 0.036 mm 2 and draws 3 μA from a 1.2 V supply, with a measured maximum inter-/intra-die variation in V be of <;1.5 mV from -40 to 125°C from two batches. Using the measured V be , Δ V be and the first-batch-only calibration parameters, the chip prototype demonstrates an untrimmed batch-to-batch inaccuracy of ± 1.5°C (3 σ ) within the same temperature range (24 samples from 2 batches).

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

This paper presents a PLL supporting diverse low-power clocking needs including wide input (6–200 MHz) and output (0.15–5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high −3dB PLL bandwidth (>40% of $f_{\mathrm{ REF}}=19.2$ MHz), and the proposed reference current generator (IrefGen) provides accurate current with <4% tolerance without the need for external components or on-chip precision resistors. IrefGen decouples PLL loop dynamics from feedback divide ratio and provides immunity to systematic capacitor variation. Power gating of switched-cap loop filter’s bias circuits results in more than 10% PLL total power savings. The PLL achieves 1.6-ps integrated RMS jitter at 4 GHz using 100-MHz reference while consuming 2.6 mW from 0.95 V. The PLL performance satisfies the stringent PCIe Gen2/3 jitter specifications without resorting to inductors.

A CMOS-Based Bidirectional Brain Machine Interface System With Integrated fdNIRS and tDCS for Closed-Loop Brain Stimulation.

A CMOS-based bidirectional brain machine interface system with on-chip frequency-domain near infrared spectroscopy (fdNIRS) and transcranial direct-current stimulation (tDCS) is designed to enable noninvasive closed-loop brain stimulation for neural disorders treatment and cognitive performance enhancement. The dual channel fdNIRS can continuously monitor absolute cerebral oxygenation during the entire tDCS process by measuring NIR light's attenuation and phase shift across brain tissue. Each fdNIRS channel provides 120dBΩ transimpedance gain at 80MHz with a power consumption of 30 mW while tolerating up to 8 pF input capacitance. A photocurrent between 10 and 450nA can be detected with a phase resolution down to 0.2°. A lensless system with subnanowatt sensitivity is realized by using an avalanche photodiode. The on-chip programmable voltage-controlled resistor stimulator can support a stimulation current from 0.6 to 2.2mA with less than 1% variation, which covers the required current range of tDCS. The chip is fabricated in a standard 130-nm CMOS process and occupies an area of 2.25 mm2.

Flux-tunable heat sink for quantum electric circuits

Superconducting microwave circuits show great potential for practical quantum technological applications such as quantum information processing. However, fast and on-demand initialization of the quantum degrees of freedom in these devices remains a challenge. Here, we experimentally implement a tunable heat sink that is potentially suitable for the initialization of superconducting qubits. Our device consists of two coupled resonators. The first resonator has a high quality factor and a fixed frequency whereas the second resonator is designed to have a low quality factor and a tunable resonance frequency. We engineer the low quality factor using an on-chip resistor and the frequency tunability using a superconducting quantum interference device. When the two resonators are in resonance, the photons in the high-quality resonator can be efficiently dissipated. We show that the corresponding loaded quality factor can be tuned from above 105 down to a few thousand at 10 GHz in good quantitative agreement with our theoretical model.

A 0.8-V Resistor-Based Temperature Sensor in 65-nm CMOS With Supply Sensitivity of 0.28 °C/V

A 0.8-V resistor-based CMOS temperature sensor in 65-nm CMOS process with low supply sensitivity is presented. The temperature-to-voltage conversion gain is maximized by utilizing two types of on-chip resistors with positive and negative temperature coefficient. Reusing the resistor sensor frontend as a reference, the voltage generator of the subsequent A/D converter inherently removes the supply dependence of temperature-to-digital conversion. A 10-bit sub-ranging A/D converter employing 5-bit amplifying interpolation D/A converter enables low-voltage and low-noise A/D conversion. Over a range of −45 °C ~ 85 °C, the proposed sensor achieves 0.12 ° ${\mathrm {C}}_{\mathrm{ rms}}$ temperature resolution with a conversion time of $10~ \mu \text{s}$ . After a 2-point calibration, the sensor achieves an inaccuracy of less than +1.6/−1 °C while consuming 47 $\mu \text{W}$ from 0.8-V supply voltage. Measured supply sensitivity is 0.28 °C/V over 0.6 ~1.2 V, which is one of the lowest ever reported among sub-1-V temperature-to-digital converter designs.