Optimization of On-Chip Meander Line Resistor by Using DOE Method

Abstract

A new analysis method for the improvement and optimization of the geometrical layout parameters associated with the on-chip n-well meander line resistor layout to have a low-quality factor (Q) and better performance operating at high frequency is investigated through factorial design experiment DOE efficient method. The factors influencing the Q-factor include the width, line length, line segment, and spacing were studied. The factorial design DOE process model was formulated using the Minitab statistical package. The result in terms of the quality factor and resistance for comparison between the proposed optimized design and conventional design layout is simulated by Sonnet electromagnetic simulation tool and validated by the theoretical mathematical prediction calculation based on an equation of lumped physical model had been presented. Results indicate that a shorter line length and line segment lead to a high impact on the improvement of the Q-factor. By the factorial design experiment, the optimized structure with a single line segment, the width of 5 µm, spacing of 1 µm, and line length of 16 µm had been established to have a lower Q-factor compared to the conventional configuration. The Q-factor was improved by 93% from 1.193 to 0.071 at the targeted 1 GHz frequency by the Sonnet EM simulation tool. The simulation result had shown comparative agreement to the theoretical mathematical predictions analysis result.