On-chip Power Research Articles

A Single-Stage Dual-Output Regulating Rectifier With Hysteretic Current-Wave Modulation

This article presents a 6.78-MHz single-stage dual-output regulating rectifier for miniaturizing the true wireless devices. The proposed rectifier topology realizes ac-dc power conversion and dual-output voltage regulation simultaneously in one single stage, using only four on-chip power transistors, thereby reducing chip area and off-chip components and improving the system power conversion efficiency. We integrate high voltage (HV) and low voltage (LV) transistors in the proposed dual-output rectifier for HV and LV output voltages, respectively. The proposed two independent three-level current-wave modulation (CWM) controllers realize voltage conversion and regulation for each output independently, with the instant transient response and no cross-regulation problem. The proposed dual-output regulating rectifier, fabricated in 0.18- μm CMOS using 1.8-/3.3-V devices, can deliver a total maximum power of 1.02 W at the dual-output voltages of 1.8 and 3.3 V. The circuit achieves a measured peak efficiency of 91.9% with an instant load-transient response for a load current step between 20 and 200 mA. The cross-regulation between the dual-output voltages is unnoticeable.

An approximate-computing empowered green 6G downlink

Approximate computing (AC) is an emerging embedded computing paradigm whereby accurate arithmetic units (i.e., adders and multipliers) of a computing platform (e.g., CPU, FPGA, ASIC etc.) are replaced by their inexact counterparts. For the applications (e.g., voice, images etc.) where the error induced by inaccurate arithmetic units remains within tolerable limits, AC is a promising technique because it leads to the design of energy-efficient computing hardware that occupies less circuit area, and has lower latency as well. This work is the first to investigate the feasibility of the AC for single-antenna and dual-antenna 6G downlink. Specifically, we consider the AC-empowered transceiver design of a 6G downlink whereby the state-of-the-art approximate/inexact arithmetic units are leverage to implement the pulse shaping filters (at the base station (BS) side) and decoders/equalizers (at the user equipment (UE) side). For simulation purpose, images and randomly generated bits are transmitted using M-ary phase shift keying scheme. To quantify the loss in arithmetic accuracy due to the AC, bit error rate (BER), structural similarity index (SSIM) and correlation coefficient (CC) are utilized as performance metrics; while to quantify the energy-efficiency benefit of the proposed AC techniques, dynamic power and on-chip power are utilized as performance metrics. Monte-Carlo results indicate up to 87% savings in dynamic power and very reasonable arithmetic accuracy (with SSIM above 93% and a CC of 99%), due to the proposed AC techniques.

Reduced Order Method for Solving Large-Scale Quadratic Eigenvalue Problems

Quadratic eigenvalue problems are frequently encountered in electromagnetic analysis of lossy dielectrics and conductors. We present a fast method for solving large-scale quadratic eigenvalue problems. The method reduces the order of the original quadratic eigenvalue problem to a small one to solve. The computational cost of the reduction is simply a small number of solutions of an underlying deterministic problem, which are obtained in linear complexity. Applications to electromagnetics-based analysis of large-scale on-chip power grids demonstrate the accuracy and efficiency of the method.

Voltage-Based Covert Channels Using FPGAs

Field Programmable Gate Arrays ( FPGAs ) are increasingly used in cloud applications and being integrated into Systems-on-Chip. For these systems, various side-channel attacks on cryptographic implementations have been reported, motivating one to apply proper countermeasures. Beyond cryptographic implementations, maliciously introduced covert channel receivers and transmitters can allow one to exfiltrate other secret information from the FPGA. In this article, we present a fast covert channel on FPGAs, which exploits the on-chip power distribution network. This can be achieved without any logical connection between the transmitter and receiver blocks. Compared to a recently published covert channel with an estimated 4.8 Mbit/s transmission speed, we show 8 Mbit/s transmission and reduced errors from around 3% to less than 0.003%. Furthermore, we demonstrate proper transmissions of word-size messages and test the channel in the presence of noise generated from other residing tenants’ modules in the FPGA. When we place and operate other co-tenant modules that require 85% of the total FPGA area, the error rate increases to 0.02%, depending on the platform and setup. This error rate is still reasonably low for a covert channel. Overall, the transmitter and receiver work with less than 3–5% FPGA LUT resources together. We also show the feasibility of other types of covert channel transmitters, in the form of synchronous circuits within the FPGA.

Graphitic Mesoporous Carbon Thin Film Prepared By Rapid Thermal Annealing for Micro-Supercapacitors

The miniaturization of electronic devices led to the advent of on-chip power sources with high energy and power density requirement. The development of such miniaturized energy devices further requires the preparation and/or processing of thin films (down to a few nanometers) of active material. Mesoporous carbon possessing both high porosity and conductivity are desired for such applications. However, obtaining thin films of mesoporous carbon on various substrates using commercially viable approaches requires further improvement and investigation. We have adapted rapid thermal annealing (RTA) as a novel approach to obtain mesoporous carbon. RTA enables rapid heating to temperatures up to 1200oC in just a few seconds and therefore provides a route for complete carbonization within a few minutes. Carbon precursor films comprised of brush block copolymers (BBCP) as sacrificial templates and phenol formaldehyde (PF) resin as a carbon source were prepared. In particular, the self-assembly of polydimethylsiloxane-b-polyethylene oxide (PDMS–b-PEO) BBCP and PF resin led to the formation of microphase-segregated film on various substrates including Si wafer, fused silica, and stainless steel. The PDMS domain in the BBCP fostered strong adhesion to the substrate even after annealing. RTA enabled complete carbonization of the precursor film within only 5 minutes, whereas conventional methods require approximately 500 minutes. Rapid processing at 1000oC resulted in the formation of mesoporous carbon with higher degree of graphitization, which is difficult to achieve with conventional carbonization method. The device prepared via RTA has a capacitance value of 7.0 mF/cm2 at 100mV/s, which is one of the highest values obtained for nanometer-thick carbon-based electrodes. These electrodes maintained a quasi-rectangular shape during the potential vs current scan, even at a scan rate of 20 V/s, which suggests that these materials are promising candidates for applications requiring very high-power density.The mesoporous carbon structure having high porosity and high conductivity can be further utilized as supports for the deposition of pseudo-capacitance materials to further boost the energy density of the device. Figure 1

A terahertz on-chip InP-based power combiner designed using coupled-grounded coplanar waveguide lines* *Project supported in part by the National Natural Science Foundation of China (Grant No. 61871072).

This article presents the design and performance of a terahertz on-chip coupled-grounded coplanar waveguide (GCPW) power combiner using a 50μm-thick InP process. The proposed topology uses two coupled-GCPW lines at the end of the input port to substitute two quarter-wavelength GCPW lines,which is different from the conventional Wilkinson power combiner and canavailably minimize the coverage area. According to the results obtained, forthe frequency range of 210–250z, the insertion losses for each two-waycombiner and four-way combiner were lower than 1.05 dB and 1.35 dB,respectively, and the in-band return losses were better than 11 dB. Moreover,the proposed on-chip GCPW-based combiners achieved a compromise in low-loss, broadband, and small-size, which can find wide applications in terahertz bands, such as power amplifiers and signal distribution networks.

Analysis of giant forward Brillouin gain enhancement in double-disk microcavities by tailoring optical forces

Stimulated Brillouin scattering in whispering gallery resonators has numerous potential applications. However, previously reported approaches are difficult to integrate and the Brillouin gain coefficient is small. We propose here a new approach to achieve giant forward stimulated Brillouin scattering (FSBS) and lasing on chip with double-disk microcavities made of silica glass. By considering the thickness of air gap to tailor optical forces especially radiation pressure in these double-disk microcavities, giant Brillouin gain enhancement can be realized in the intermode FSBS. The numerical simulation results indicate that for double-disk microcavity within the radius range of 50 μm, stimulated Brillouin scattering gain is ten times larger than that of single-disk microcavity up to 74.3 m−1W−1 with Rayleigh acoustic mode and 102 to 103 times larger up to 6361.19 m−1W−1 with symmetric Lamb acoustic mode. Correspondingly, the on-chip pump power threshold of Brillouin lasing can be reduced to 55 μW with the slope efficiency of 8.0%. Our proposed double-disk microcavities offer an effective and simple method to implement Brillouin lasing and can find versatile applications of acousto-optic interaction on all-integrated CMOS compatible chip.

Real-Time Generation of NHS-OFDM Signal for Direct-Modulation and Direct-Detection PON

Orthogonal frequency-division multiplexing-based passive optical networks (OFDM-PON) can provide high spectral efficiency and flexible two-dimensional bandwidth allocation by assigning subcarriers (SCs) and time slots. The direct-modulation and direct-detection (DM-DD) OFDM with Hermitian symmetry constraint has simple hardware implementation, low cost, and low power consumption compared to coherent detection and is more suitable for cost-sensitive PON. In such a Hermitian symmetric optical OFDM (HS-OFDM), only half of the SCs can be used to carry user data, and thus inverse fast Fourier transform (IFFT) and FFT sizes are inefficient in the viewpoint of hardware implementation. In this work, we use a single field programmable gate array and digital-to-analog converter to implement an HS-free OFDM (NHS-OFDM) transmitter without digital/analog up-conversion. We compare the on-chip resource overhead and power consumption between real-time HS-OFDM and NHS-OFDM transmitters under the same bandwidth granularity and data transmission rate. The registers, look-up tables and multipliers are saved up to 45%, 49.5% and 58.7%, respectively. Besides, the on-chip power consumption is also reduced by 15%. Moreover, the two real-time transmitters are experimentally investigated in a short-reach DM-DD transmission system. A similar bit error rate performance can be achieved after 20/50/70 km standard single-mode fiber transmission.

Ultralow-threshold thin-film lithium niobate optical parametric oscillator

Materials with strong second-order ( χ ( 2 ) ) optical nonlinearity, especially lithium niobate, play a critical role in building optical parametric oscillators (OPOs). However, chip-scale integration of low-loss χ ( 2 ) materials remains challenging and limits the threshold power of on-chip χ ( 2 ) OPO. Here we report an on-chip lithium niobate optical parametric oscillator at the telecom wavelengths using a quasi-phase-matched, high-quality microring resonator, whose threshold power ( ∼ 30 µ W ) is 400 times lower than that in previous χ ( 2 ) integrated photonics platforms. An on-chip power conversion efficiency of 11% is obtained from pump to signal and idler fields at a pump power of 93 µW. The OPO wavelength tuning is achieved by varying the pump frequency and chip temperature. With the lowest power threshold among all on-chip OPOs demonstrated so far, as well as advantages including high conversion efficiency, flexibility in quasi-phase-matching, and device scalability, the thin-film lithium niobate OPO opens new opportunities for chip-based tunable classical and quantum light sources and provides a potential platform for realizing photonic neural networks.

Hybrid dual-gain tunable integrated InP-Si3N4 external cavity laser.

We present a hybrid dual-gain integrated external cavity laser with full C-band wavelength tunability. Two parallel reflective semiconductor optical amplifier gain channels are combined by a Y-branch in the Si3N4 photonic circuit to increase the optical gain. A Vernier ring filter is integrated in the Si3N4 photonic circuit to select a single longitudinal mode and meanwhile reduce the laser linewidth. The side-mode suppression ratio is ∼67 dB with a pump current of 75 mA. The linewidth of the unpackaged laser is 6.6 kHz under on-chip output power of 23.5 mW. The dual-gain operation of the laser gives higher output power and narrower linewidth compared to the single gain operation. It is promising for applications in optical communications and light detection and ranging systems.

Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU

Recent breakthroughs in Neural Networks (NNs) led to significant accuracy improvements of several machine learning applications such as image classification and voice recognition. However, this accuracy improvement comes at the cost of an immense increase in computation demands. NNs became one of the most common and computationally intensive workloads in today's datacenters. To address these computational demands, Google announced in 2016 the Tensor Processing Unit (TPU), an advanced custom ASIC accelerator for NN inference. Two new TPU versions (v2 and v3) followed in 2017 and 2018 that support also training. Google TPUv3 packs an immense processing power ( <inline-formula><tex-math notation="LaTeX">$\mathrm{90TFLOPS}$</tex-math></inline-formula> per chip) in a tiny and condensed area, leading to very high on-chip power densities and thus excessive temperature. In this article, superlattice thermoelectric cooling, which is one of the emerging on-chip cooling, is considered as an advanced cooling example for Google TPU and we investigate the impact of Negative Capacitance FET (NCFET), which is one of the recent emerging technologies, on the cooling and efficiency of TPU. Through full-chip design, of the computational core of the TPU, based on <inline-formula><tex-math notation="LaTeX">$14\mathrm{nm}$</tex-math></inline-formula> Intel FinFET technology and multiphysics temperature simulations, we demonstrate that NCFET can significantly minimize the required cooling-cost. More than 4000 NCFET configurations are evaluated in order to traverse the entire design space defined by the thickness of the ferroelectric layer of NCFET, the operating voltage, cooling, and the operating frequency, in addition to all possible FinFET's configurations. Moreover, our experimental evaluation shows that by eliminating the cooling cost, NCFET delivers 2.8x higher efficiency compared to the conventional FinFET baseline.

Design and Characterization of (140–220) GHz Frequency Compensated Power Detector

This article presents the design and characterization of a real-time frequency-compensated power detector (PD), based on NMOS transistor, integrated in SiGe 55-nm BiCMOS technology from STMicroelectronics, and dedicated to on-chip power detection in the G-band frequencies. An innovative simple circuit (named attenuator) is designed in order to compensate the variation of the voltage sensitivity value with frequency, which is established by exhibiting lower attenuation (smaller real part impedance) at higher frequencies. As a result, the measured sensitivity value is compensated with a small variation (1800 V/W±10%) over the frequency band (140-220) GHz. To the best of the authors' knowledge, this detector is the first design which proposes a real-time frequency compensation at such high- and large-frequency bands. The attenuator was also designed to exhibit an inductive impedance (in the G-band) in order to compensate the capacitive effect of the NMOS, which helps to use smaller NMOS size and, therefore, obtain a higher sensitivity value. Compared to recent works, our detector exhibits a performance belong the current state-of-the-art with a very low noise equivalent power (NEP) value 4.56 pW/ √Hz and a relatively high voltage sensitivity value.

3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance

3-D stacks of complimentary metal-oxide-semiconductor (CMOS) integrated circuit (IC) chips for security applications monolithically embed backside buried metal (BBM) routing with low series impedance and high decoupling capability in a power delivery network (PDN), thanks to distributed capacitances over a full-chip backside area. The 3-D Si demonstrator integrating cryptographic engines was fabricated in a 0.13-μm CMOS technology with post-Si wafer-level BBM Cu processing with 10, 15, and 10 μm of thickness, linewidth, and space, respectively, along with through Si vias (TSVs) with 10 and 40 μm of diameter and depth, respectively. The capacitance of 0.18 nF/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in the effective backside area of 71 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> suppressed dynamic IR drops in 10% and 59% for the single chip and four chip stack samples, respectively, during the operation of a 3.9 M-gate crypto core at 30 MHz. On-chip power noise monitoring (OCM) was applied in these measurements. The 3-D BBM PDN also effectively reduces power side channel information leakage, which is evaluated by 14× increase in the number of externally observed electromagnetic (EM) noise waveforms to attain the t-test value of larger than 4.5.

FPGA Implementation for CNN-Based Optical Remote Sensing Object Detection

In recent years, convolutional neural network (CNN)-based methods have been widely used for optical remote sensing object detection and have shown excellent performance. Some aerospace systems, such as satellites or aircrafts, need to adopt these methods to observe objects on the ground. Due to the limited budget of the logical resources and power consumption in these systems, an embedded device is a good choice to implement the CNN-based methods. However, it is still a challenge to strike a balance between performance and power consumption. In this paper, we propose an efficient hardware-implementation method for optical remote sensing object detection. Firstly, we optimize the CNN-based model for hardware implementation, which establishes a foundation for efficiently mapping the network on a field-programmable gate array (FPGA). In addition, we propose a hardware architecture for the CNN-based remote sensing object detection model. In this architecture, a general processing engine (PE) is proposed to implement multiple types of convolutions in the network using the uniform module. An efficient data storage and access scheme is also proposed, and it achieves low-latency calculations and a high memory bandwidth utilization rate. Finally, we deployed the improved YOLOv2 network on a Xilinx ZYNQ xc7z035 FPGA to evaluate the performance of our design. The experimental results show that the performance of our implementation on an FPGA is only 0.18% lower than that on a graphics processing unit (GPU) in mean average precision (mAP). Under a 200 MHz working frequency, our design achieves a throughput of 111.5 giga-operations per second (GOP/s) with a 5.96 W on-chip power consumption. Comparison with the related works demonstrates that the proposed design has obvious advantages in terms of energy efficiency and that it is suitable for deployment on embedded devices.

Octave-spanning Kerr frequency comb generation with stimulated Raman scattering in an AlN microresonator.

Octave-spanning optical frequency combs (OFCs) are essential for various applications, such as precision metrology and astrophysical spectrometer calibration. In this Letter, we demonstrate, for the first time to our knowledge, the generation of octave-spanning Kerr frequency combs ranging from 1150 to 2400 nm in aluminum nitride (AlN) microring resonators, by pumping the TM00 modes at 250 mW on-chip power. By simply adjusting the pump detuning, we observe the transition and coexistence of Kerr OFC and stimulated Raman scattering. For the TE00 mode in the same device, a broadband Raman-assisted frequency comb is demonstrated by adjusting the pump power and tuning. These results indicate a crucial development for the fundamentals of nonlinear dynamics and comb applications in AlN.

Experimental Measurements of a Low Power CMOS Analog MPPT Power Conditioning Circuit for Energy Harvesting Applications

This paper presents the complete measured performance and characterization of a fabricated power conditioning integrated circuit for energy harvesters with on-chip maximum power point tracking (MPPT) and external energy storage. This ultra-low power circuit employs an AC/DC-to-DC converter compatible with both AC and DC voltage energy harvesters. The MPPT design follows the perturbation and observation algorithm. This MPPT is capable of tracking the maximum power point of types of energy harvesters. The circuit is implemented using the AMS CMOS 0:35 μm high voltage technology and all the circuit blocks use analog electronic techniques, with the transistors operating in the sub-threshold region, in order to obtain a minimum power consumption. This power conditioning circuit consumes less than 2 μW while featuring an input voltage range of -0:5V to -50V and a power range from 10 μW to 200mW.

Hybrid printed three-dimensionally integrated micro-supercapacitors for compact on-chip application

The emerging internet of things requires autonomous and ubiquitous on-chip devices with wireless interconnectivity. On-chip power is required to meet the miniaturization requirement, and an integrated on-chip micro-supercapacitor has enormous potential to meet this requirement owing to its high-power density and long cycle life. However, the two-dimensional expansion of the current co-planer design paradigm of micro-supercapacitors, such as the interdigital layout, hinders the on-chip integration density, resulting in a significant consumption of precious chip footprint and an insufficient energy density. This article reports on the use of a three-dimensional framework along with a hybrid printing strategy to fabricate devices entirely without any post-processing, and highly integrated three-dimensional micro-supercapacitors were printed as proof of concept. The micro-supercapacitors exhibit more than 25 times areal capacitance than the interdigital ones (76 mF/cm2 vs 2.9 mF/cm2) due to their three-dimensional feature. Moreover, it can provide new functions to achieve adjustable voltage and capacitance flexibility within one device's footprint area. This approach can also enable devices on different substrates. An ultraviolet sensor was integrated with and powered by the three-dimensional micro-supercapacitors on polyimide to demonstrate the compact on-chip application. The three-dimensional framework offers a general solution to the on-chip integration challenges of micro-supercapacitors. Moreover, it can be extended to new materials or even other electronics units, highlighting the promise of further miniaturized and powerful micro-electronics.

Bright 547-dimensional Hilbert-space entangled resource in 28-pair modes biphoton frequency comb from a reconfigurable silicon microring resonator

High-dimensional entanglement provides valuable resources for quantum technologies, including quantum communication, quantum optical coherence tomography, and quantum computing. Obtaining a high brightness and dimensional entanglement source has significant value. Here we utilize a tunable asymmetric Mach–Zehnder interferometer coupled silicon microring resonator with 100 GHz free spectral range to achieve this goal. With the strategy of the tunable coupler, the dynamical and extensive tuning range of quality factors of the microring can be obtained, and then the biphoton pair generation rate can be optimized. By selecting and characterizing 28 pairs from a more than 30-pair modes biphoton frequency comb, we obtain a Schmidt number of at least 23.4 and on-chip pair generation rate of 19.9 MHz/mW2 under a low on-chip pump power, which corresponds to 547 dimensions Hilbert space in frequency freedom. These results will prompt the wide applications of quantum frequency comb and boost the further large density and scalable on-chip quantum information processing.

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Conventional power delivery networks (PDNs) and power management techniques using off-chip power converters with bulky passive components cannot meet the ever-evolving power delivery requirements of high-performance modern system-on-chips (SoCs). In SoCs, heterogeneous components, including multi-core processors and mixed-signals peripheral circuits, require state-of-the-art PDNs to provide high-quality power-on-demand with minimum latency, simultaneously achieving the small-factor, high conversion efficiency, and minimum current consumption. To satisfy these power delivery requirements, various PDNs have been developed over the past decades, such as the conventional architectures using off-chip power converters, architectures using in-package power converters and fully-integrated power converters, and heterogeneous architectures (off-chip power converters and on-chip regulators). This paper reviews these architectural advancements of the PDNs and their advantages and limitations, which leads us to discuss a heterogeneous PDN structure consisting of a highly efficient off-chip switching-mode power converter and multiple highly precise small linear regulators integrated on chip at point-of-load locations. The heterogeneous PDN has been proved one of the most suitable architectures to achieve high-quality fine-grained on-chip power delivery and management in SoCs. This paper also discusses unified voltage and frequency regulators (UVFRs), which support dynamic-variation-aware dynamic voltage and frequency scaling (DVFS) for fine-grained power management in multi-core processors. Based on the UVFR, we propose a modified heterogeneous PDN using frequency-referenced digital low-dropout regulators (FR-DLDOs) for more efficient DVFS, eliminating the need for band-gap circuits to provide reference voltages. As an exemplary implementation of FR-DLDO for this PDN, we present an FR-DLDO with a transient-boost control, which accelerates the transient response. The transient-boost control is activated dynamically only when an abrupt change happens out of the steady state. The implemented FR-DLDO fabricated in a 40-nm CMOS process outperforms other FR-DLDOs in the figure-of-merit and peak power efficiency while driving 40 mA of load current.

A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits

With the increase of density and complexity of high performance integrated circuits and systems, including many-core chips and system-on-chip (SoC), it is becoming difficult to meet the power delivery and regulation requirements with off-chip regulators. The off-chip regulators become a less attractive choice because of the higher overheads and complexity imposed by the additional wires, pins, and pads. The increased $I^{2}R$ loss makes it challenging to maintain the integrity of different voltage domains under a lower supply voltage environment in the smaller technology nodes. Fully integrated on-chip voltage regulators have proven to be an effective solution to mitigate power delivery and integrity issues. Recently, there has been a surge of interest among the academic and industrial research communities to explore and design different types of on-chip voltage regulators. This survey presents a brief overview of the on-chip power delivery system and the classification and working principles of on-chip voltage regulators. The main focus of this review paper is to provide a comprehensive study of two of the most promising on-chip voltage regulators – (i) the low-drop-out (LDO) regulator and (ii) the switched-capacitor (SC) regulator. This article elaborates on the design specifications, optimization techniques, advantages, and limitations of LDO and SC type on-chip voltage regulators.