On-chip Power Distribution Network Research Articles

Superconducting Electronic–Photonic Platform for HEB-Based Terahertz Spectrometers

Terahertz photonic integrated circuits are becoming popular in ultrafast on-chip signal generation and processing. They outperform assemblies of electronic devices making use of metallic waveguides in term of both fabrication complexity and system losses. In this study, we report on a nearly all-dielectric hot electron bolometer mixer compatible with the technology of integrated Si photonic crystals. The developed on-chip power distribution networks ensure input losses of 2.4 dB and far-field radiation patterns with a gain of 12.1 dB and a side lobe level below −11 dB. The mixer is designed for spectral measurements at 2.7 THz. It can be used either as a part of an on-chip spectrometer or as a standalone device.

On-Chip Power Integrity Simulation Using LSI-Core Macromodels Considering Voltage Fluctuations Caused by Inter-Function-Block Interference

When designing on-chip power distribution networks (PDNs) of a large-scale integrated circuit (LSI), power integrity (PI) must be ensured not to cause malfunctions. LSI-core macromodels are expected to be used for fast PI simulation. When building LSI-core macromodels from design information, the impedance and equivalent current sources are often extracted for each function block or smaller operating block. In the stage of modeling function blocks, the layout and operation of the surrounding function blocks are not fixed, so equivalent current sources of the macromodel of each function block are extracted under ideal power supply conditions. However, in an actual LSI, the on-chip PDNs have a certain impedance and the power supply voltage of each function block is not ideal dc voltage because of its own operation and the interference from the operation of surrounding function blocks in the same power domain. Since operating currents of transistors are affected by on-chip supply voltage fluctuations, this effect must be taken into account when simulating the PI of the entire LSI or the simulation accuracy will degrade. This article proposes a PI simulation method using LSI-core macromodels that takes into account on-chip supply voltage fluctuations due to the interference between function blocks in the same power domain. To verify the proposed method, a test chip with several function blocks was built, and it was confirmed that the proposed method can simulate PI with high accuracy.

PEEC Modeling in 3D IC/Packaging Applications Based on Layered Green's Functions

A circuit modeling application for 3D IC/packages is proposed in this paper. The method is based on the partial element equivalent circuit (PEEC) method and layered Green's functions (LGF). The LGFs are calculated from the discrete complex image method with three terms, direct coupling, complex images, and surface wave, extracted to analyze the wave behaviors. The dominant terms for the LGFs are analyzed for four canonical stack-ups in 3D IC/packaging systems. Analytical formulas that include the contribution of the complex images calculated from the LGFs are used for the partial capacitance calculation. A fast-modeling approach is proposed by applying the LGF in PEEC using three acceleration treatments to handle the 3D IC/packaging geometry without sacrificing accuracy. An on-chip power distribution network (PDN) geometry is used to illustrate and validate the method.

Impedance modeling and analysis of multi-stacked on-chip power distribution network in 3D ICs

An accurate impedance modeling of a multi-stacked on-chip power distributed network (PDN) based on through-silicon-vias (TSVs) is vitally important to estimate the electrical performance in three-dimensional integrated circuits (3D ICs). This paper proposes a method for calculating the impedance matrix of the multi-stacked on-chip PDN, which mainly consists of arbitrarily distributed TSVs and grid-type on-chip PDNs. First, a real stack-up structure of a multi-stacked on-chip PDN is separated into discrete components intentionally. Then, the equivalent lumped circuit models of all discrete components are assembled into a whole to build the transmission matrix of the multi-stacked on-chip PDN through the relationship between the nodal voltage and the nodal current. Finally, the impedance matrix can be derived through the transmission matrix. In this paper, the coupling of the arbitrarily distributed TSVs and the distributional effect of the on-chip PDN are considered in the impedance matrix through the transmission matrix method (TMM). The proposed method replaces the simulation of the complex equivalent circuit model with the matrix calculation. The verification results show that the deviation of resonant frequency is about 6 $$\%$$ and the conversation of the simulation time is about 99.9 $$\%$$ compared with the HFSS model. It can accurately and quickly calculate the impedance of the multi-stacked on-chip PDN.

Compensating Method of Equivalent Current Sources of LSI-Core Macromodel Considering Voltage Fluctuations in On-Chip Power Distribution Network

Electro-magnetic compatibility (EMC) macromodels of a large-scale integrated (LSI) circuit core have been proposed to predict conducted RF emission and power integrity issues not only on a printed circuit board but also inside an LSI. They are equivalent circuit models that consist of lumped element impedance blocks of an LSI-core and equivalent current sources expressing internal switching activities. In conventional macromodeling, equivalent current sources have been extracted under ideal power supply conditions, i.e., with constant supply voltage. However, there exists transient supply voltage fluctuations in an actual on-chip power distribution network (PDN), and the operating current and its equivalent current sources are expected to vary with such fluctuations. Such issues with transient supply voltage fluctuations have not been extensively investigated. We propose a method of compensating the equivalent current sources of a macromodel by introducing amplitude and time correction factors, taking into account the voltage fluctuations in an on-chip PDN.

Voltage-Based Covert Channels Using FPGAs

Field Programmable Gate Arrays ( FPGAs ) are increasingly used in cloud applications and being integrated into Systems-on-Chip. For these systems, various side-channel attacks on cryptographic implementations have been reported, motivating one to apply proper countermeasures. Beyond cryptographic implementations, maliciously introduced covert channel receivers and transmitters can allow one to exfiltrate other secret information from the FPGA. In this article, we present a fast covert channel on FPGAs, which exploits the on-chip power distribution network. This can be achieved without any logical connection between the transmitter and receiver blocks. Compared to a recently published covert channel with an estimated 4.8 Mbit/s transmission speed, we show 8 Mbit/s transmission and reduced errors from around 3% to less than 0.003%. Furthermore, we demonstrate proper transmissions of word-size messages and test the channel in the presence of noise generated from other residing tenants’ modules in the FPGA. When we place and operate other co-tenant modules that require 85% of the total FPGA area, the error rate increases to 0.02%, depending on the platform and setup. This error rate is still reasonably low for a covert channel. Overall, the transmitter and receiver work with less than 3–5% FPGA LUT resources together. We also show the feasibility of other types of covert channel transmitters, in the form of synchronous circuits within the FPGA.

Interview

Wen-Sheng Zhao from Hangzhou University, China, talks to Electronics Letters about the paper ‘Novel electromagnetic bandgap structure for wideband suppression of simultaneous switching noise’, page 1243 Wen-Sheng Zhao My research fields include interconnect modelling, multiphysics simulations and microwave sensor design. My major research topic is signal and power analysis of silicon via (TSV)-based 3D integrated systems. In recent years, the fourth industry revolution has shown an urgent need to develop next generation memory modules. As a key technology of industry 4.0, TSV-based high-bandwidth memory (HBM) has attracted a lot of interest from both the research and industrial worlds. To guarantee the system performance, it is necessary to perform signal/power/thermal integrity analysis for an HBM module. We are currently working on the issues related to the physical design of HBM modules (such as TSV modeling, equaliser design, and power noise suppression). Modern circuits are developing towards miniaturisation, high frequency and low power consumption, which puts strict constraints on the signal and power integrity design. For example, the operating voltages are continuously lowered, thereby limiting noise margin in power distribution network (PDN). Under such circumstances, power/ground noise is becoming a serious problem. To resolve this issue, various techniques including decoupling capacitor and electromagnetic bandgap (EBG) have been proposed and are under study. In comparison with decoupling capacitor, EBG structure can provide wideband noise suppression, and has been widely explored in the chip, package, and board. To improve the system performance, it is always desirable to increase the stopband bandwidth and rejection level of EBG structure. In this Letter, a power plane with coplanar EBG etched in the S-bridge EBG was proposed. With the proposed EBG structure, an ultrawide bandgap from 0.28 to 25 GHz with a high suppression level of -45 dB was achieved. Moreover, the signal integrity performance of the proposed EBG power plane was examined. The signal integrity can be ensured by utilising differential traces as the transmission structure. The proposed design can be used to reduce power/ground noise efficiently for mixed signal systems. We expect the proposed design to provide performance improvements in various mixed-signal systems in the immediate future. Currently, we are also working on developing EBG structures for silicon interposer and on-chip PDN. In the longer term, we expect that the EBG structures can be further explored and used in the physical design optimisation of HBM systems. As the clock frequency of the circuit system is continuously increased, the frequency of the simultaneous switching noise (SSN) also increases. However, the low-frequency components of the noise are not reduced accordingly. Therefore, the major issue we faced was developing a wide stopband EBG structure with a low cutoff frequency. Moreover, as grooves etched on the power/ground plane have an adverse impact on the signal transmission, we had to pay special attention to ensure signal integrity in the EBG design procedure. When we began studying TSV technologies, there was very little real-world deployment. Although several semiconductor giants such as Samsung presented some TSV based memory modules, these systems remained in the laboratory stage. Nowadays, TSV technology has matured, and the TSV-based HBM modules have been used in many graphics processing units since 2015. We are currently working on the physical design and optimisation (including signal and power integrity analysis) for TSV-based integrated systems. We have seen the introduction of many kinds of techniques (e.g., EBG, equaliser, differential signaling, and active decoupling) which will be helpful for future designs. There is no doubt that further improvements are always desirable to promote wide applications of TSV based integrated systems.

On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors

The increasing power density and, therefore, current consumption of high-performance integrated circuits (ICs) results in increased challenges in the design of a reliable and efficient on-chip power delivery network. In particular, meeting the stringent on-chip impedance of the IC requires circuit and system techniques to mitigate the high-frequency noise that results due to resonance between the package inductance and the on-chip capacitance. A novel circuit technique is proposed to suppress high-frequency noise through the use of a hyperabrupt junction tuning varactor diode as a decoupling capacitor (decap) for noise critical functional blocks. With the proposed circuit technique, the voltage droops and overshoots on the on-chip power distribution network are suppressed by up to 60% as compared with MIM or deep trench decaps of the same capacitance. In addition, there is no added latency to react to power supply noise, and there is no degradation to circuit performance as compared with existing techniques in commercial products and literature.

Inductance Extraction of Grid Power Distribution Network

For the package or on-chip power distribution network (PDN) design, plane metals are usually adopted. In this paper, we propose a closed-form grid metals solution to calculate the inductance of such grid PDN for the frequencies below its first antiresonant frequency. First, the grid PDN is equivalent to a plane PDN based on the equivalent circuit of their unit cells. Furthermore, the equivalent plane PDN is simplified as an RLCG lumped circuit, where ${L}$ is the inductance of the grid PDN. Finally, the inductance of the grid PDN is obtained by the mode analysis of the equivalent plane PDN with a modified modal function. The proposed method is scalable, which can calculate the grid PDNs with the size from micrometer to centimeter. To verify the proposed method, a centimeter grid PDN is fabricated. The inductance obtained by the proposed method has a good agreement with that obtained by measurement and 3-D full-wave simulation. The proposed method can also be expanded to the case that the grid PDN has load impedances. In comparison with the numerical methods, the proposed method can give a more easy-to-understand explanation of the new antiresonant frequency produced by the load impedance.

Analysis of Impedance & Supply Noise for Power Distribution Networks in IC Using CM

With increasing design complexity, as well as continued scaling of supplies, the design and analysis of power distribution networks poses a difficult problem in modern IC design. We propose several closed-form solutions for power distribution network optimization and analysis which explicitly take into consideration the mesh topology. An RLC model for on-chip power distribution networks is presented for array and wire bonded integrated circuits including inter block decoupling capacitors and impedances. One of the more common design techniques for power distribution networks PDN is the determination of the impedance & supply noise. Current-mode technique is used. By using this current mode technique noise and impedance, voltage is analyzed.

Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors

An $RLC$ model for on-chip power distribution networks (PDN) is presented for array and wire-bonded integrated circuits including interblock decoupling capacitors and C4 impedances. From the model, the supply noise produced by switching blocks as well as the impedance to ac ground as seen from any point of the circuit are calculated as a function of frequency and PDN parameters. The proposed method to perform such calculation allows optimizing relevant PDN design parameters, such as number, size, and location of supply/ground pads and location of interblock decoupling capacitors, and width and pitch of metal tracks. The PDN model and impedance calculations are validated by comparing their results with SPICE simulations, giving a maximum error of less than 1%.

Quantifying the effect of local interconnects on on-chip power distribution

Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.

On-chip linear voltage regulator module (VRM) effect on power distribution network (PDN) noise and jitter at high-speed output buffer

In this paper, the reduction of power distribution network noise and jitter at high-speed output buffer by using on-chip linear voltage regulator module circuit is introduced and analyzed. The transient response of typical on-chip linear VRM circuit is analyzed in power gating condition. When the on-chip linear VRM circuit is inserted between on-chip PDN and operating high-speed output buffers, the on-chip PDN noise and jitter at output buffer are significantly reduced. The larger on-chip decoupling capacitor leads to the lower PDN noise generated by on-chip linear VRM circuit. The on-chip linear VRM also reduces the impact of the aggressor buffer to the victim buffer in different PDN, resulting in the improved performance of the victim buffer. Reduction of PDN noise and jitter at output buffer using on-chip linear VRM are validated based on SPICE simulation with 110 nm CMOS technology library.

The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements

A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement, which currently predominates, as well as equilateral triangular and hexagonal arrangements. In agreement with the findings in the literature and with physical and SPICE models, the equilateral triangular power pad arrangement is found to minimize the maximum voltage drop. This headline finding is a consequence of relatively simple formulas for the voltage drop, with explicit error bounds, which are established using complex analysis techniques, and elliptic functions in particular.

Initial Designs of an on-Chip EMI Sensor Array

The purpose of the on-chip EMI sensor array (OCEMISA) is to measure the 2-dimension profile of the EMI voltage in the on-chip power distribution network in real time. The feedback signal from a senser cell should reflect only its local EMI. Signals have to be grouped carefully. This paper presents two different designs of the OCEMISA. In the first design, sensor cell generates regular pulses as feedback. The time domain waveform is monitored. In the second design, the supply noise generated by the sensor cell is utilized as feedback. The spectrum is monitored. Designs are implemented with FPGA for validation check. Measurement results show that feedback signals faces synchronization and instability problems. Those problems come from the IC process variation and are influenced by the feedback scheme. With the presentation and analysis of those problems, the paper is intent to provide optimization directions to make OCEMISA practical.

State-Dependence of On-Chip Power Distribution Network Capacitance

SUMMARY In this paper, the measurement of capacitance variation, of an on-chip power distribution network (PDN) due to the change of internal states of a CMOS logic circuit, is studied. A state-dependent PDNcapacitance model that explains measurement results will be also proposed. The model is composed of capacitance elements related to MOS transistors, signal and power supply wires, and substrate. Reflecting the changes of electrode potentials, the capacitance elements become state-dependent. The capacitive elements are then all connected in parallel between power supply and ground to form the proposed model. By using the proposed model, state-dependence of PDN-capacitances for different logic circuits are studied in detail. The change of PDN-capacitance exceeds 12% of its total capacitance in some cases, which corresponds to 6% shift of antiresonance frequency. Consideration of the state-dependence is important

IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption

A compact IR-drop model for on-chip power distribution networks in array and wire-bonded ICs is analyzed. Chip dimensions, size, and location of the supply pads, metal coverage, piecewise distribution of IC consumption, and the resistance between the pads and the power supply are considered to obtain closed-form expressions for the IR-drop. The IR-drop model is validated by comparing its results with electrical simulations. The obtained error is in the range of 1%.

Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects

In this paper, we propose a model for 3-D stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3-D memory ICs that includes the effects of power/ground TSVs (P/G TSVs), on-chip decoupling capacitors (on-chip decaps), and the silicon substrate. In the modeling procedure of 3-D stacked on-chip PDNs, the distributed RLGC-lumped model of an on-chip PDN, including the effects of the on-chip decaps and silicon substrate, is proposed. Additionally, the RLGC-lumped model of a P/G TSV pair is introduced. The proposed model of the 3-D stacked on-chip PDN combines the proposed models of on-chip PDNs with the models of P/G TSV pairs in a hierarchical order with a segmentation method. The proposed models of the on-chip PDN and 3-D stacked on-chip PDN are successfully validated by simulations and measurements up to 20 GHz. Additionally, with these models, the impedances of the 3-D stacked on-chip PDNs are analyzed with respect to the variations in the number of P/G TSV pairs, the capacitance of on-chip decaps, and the height of an interlayer dielectric layer between the on-chip PDN and silicon substrate. These variations critically affect the impedance of the 3-D stacked on-chip PDN by changing the capacitance and inductance of the PDN.

Latency Insertion Method (LIM) for DC Analysis of Power Supply Networks

Process scaling in modern integrated circuits has led to multiple signal and power integrity issues. In particular, ensuring reliable performance of on-chip power delivery systems has become a major design challenge. Rigorous analysis and simulations are required at the design stage to ensure proper functionality of an on-chip power supply. This puts a strain on existing numerical tools due to the sheer size of the power grids. In this paper, a fast circuit simulation technique based on the latency insertion method (LIM) is proposed for the steady-state analysis of large-scale circuits, such as on-chip power distribution network. The proposed method is shown to be very efficient for modeling of networks with very large numbers of nodes. The comparison with one of the well-established methods used for the power grid analysis today, the Random-Walk algorithm, shows that LIM is almost two orders of magnitude faster.

On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network

We present a new asymptotic formula for the maximum static voltage in a simplified model for on-chip power distribution networks of array bonded integrated circuits. In this model the voltage is the solution of the Poisson's equation in an infinite planar domain whose boundary is an array of circular pads of radius ϵ, and we deal with the singular limit ϵ → 0 case. In comparison with approximations that appear in the electronics engineering literature, our formula is more complete, since we have obtained terms up to order ϵ15. A procedure will be presented to compute all the successive terms, which can be interpreted by using multipole solutions of equations involving spatial derivatives of δ-functions. To deduce the formula, we use the method of matched asymptotic expansions. Our results are completely analytical and we make an extensive use of special functions and the Gauss constant G.