On-chip Power Dissipation Research Articles

Nanoelectromechanical Control of Spin-Photon Interfaces in a Hybrid Quantum System on Chip.

Color centers (CCs) in nanostructured diamond are promising for optically linked quantum technologies. Scaling to useful applications motivates architectures meeting the following criteria: C1 individual optical addressing of spin qubits; C2 frequency tuning of spin-dependent optical transitions; C3 coherent spin control; C4 active photon routing; C5 scalable manufacturability; and C6 low on-chip power dissipation for cryogenic operations. Here, we introduce an architecture that simultaneously achieves C1-C6. We realize piezoelectric strain control of diamond waveguide-coupled tin vacancy centers with ultralow power dissipation necessary. The DC response of our device allows emitter transition tuning by over 20 GHz, combined with low-power AC control. We show acoustic spin resonance of integrated tin vacancy spins and estimate single-phonon coupling rates over 1 kHz in the resolved sideband regime. Combined with high-speed optical routing, our work opens a path to scalable single-qubit control with optically mediated entangling gates.

Digital Control of a Superconducting Qubit Using a Josephson Pulse Generator at 3 K.

Scaling of quantum computers to fault-tolerant levels relies critically on the integration of energy-efficient, stable, and reproducible qubit control and readout electronics. In comparison to traditional semiconductor-control electronics (TSCE) located at room temperature, the signals generated by rf sources based on Josephson-junctions (JJs) benefit from small device sizes, low power dissipation, intrinsic calibration, superior reproducibility, and insensitivity to ambient fluctuations. Previous experiments to colocate qubits and JJ-based control electronics have resulted in quasiparticle poisoning of the qubit, degrading the coherence and lifetime of the qubit. In this paper, we digitally control a 0.01-K transmon qubit with pulses from a Josephson pulse generator (JPG) located at the 3-K stage of a dilution refrigerator. We directly compare the qubit lifetime T 1, the coherence time , and the thermal occupation P th when the qubit is controlled by the JPG circuit versus the TSCE setup. We find agreement to within the daily fluctuations of ±0.5 μs and ±2 μs for T 1 and , respectively, and agreement to within the 1% error for P th. Additionally, we perform randomized benchmarking to measure an average JPG gate error of 2.1 × 10-2. In combination with a small device size (< 25 mm2) and low on-chip power dissipation (≪100 μW), these results are an important step toward demonstrating the viability of using JJ-based control electronics located at temperature stages higher than the mixing-chamber stage in highly scaled superconducting quantum information systems.

Efficient Simulation of Thermo-Mechanical Stress in the On-Chip Metallization of Integrated Power Semiconductors

Integrated power semiconductors are often used for applications with cyclic on-chip power dissipation. This leads to repetitive self-heating and thermo-mechanical stress, causing fatigue on the on-chip metallization and possibly destruction by short circuits. Because of this, an accurate simulation of the thermo-mechanical stress is needed already during the design phase to ensure that lifetime requirements are met. However, a detailed thermo-mechanical simulation of the device, including the on-chip metallization is prohibitively time-consuming due to its complex structure, typically consisting of many thin metal lines with thousands of vias. This paper introduces a two-step approach as a solution for this problem. First, a simplified but fast simulation is performed to identify the device parts with the highest stress. After, precise simulations are carried out only for them. The applicability of this method is verified experimentally for LDMOS transistors with different metal configurations. The measured lifetimes and failure locations correlate well with the simulations. Moreover, a strong influence of the layout of the on-chip metallization lifetime was observed. This could also be explained with the simulation method.

Type III compensated voltage mode line feedforward synchronously rectified boost converter for driving Class D audio H-bridge to deliver 7 W peak power into an 8 $\Omega$ speaker

In this paper, a circuit topology for a synchronously rectified boost converter aimed to act as a power supply for a Class D H-bridge that would deliver up to 7 W peak power into an 8 Omega speaker is presented. The design is implemented in a submicron BCD process technology. Some of the challenges in this design are as follows. The first challenge was to optimise the design such that it would not cause on-chip power dissipation levels that would go beyond acceptable levels for Wafer Level Chip Scale Package (WLCSP), which is a commonly used package for space constrained applications in portable spaces. To address this issue, a Class G mode of operation to deliver multiple boost voltage levels has been proposed. Second, due to the chosen submicron BCD process lacking some devices such as zener diodes to clamp maximum voltages that active device gate-source and/or drain-source terminals in case of transient or normal operating conditions of the circuit, new ways of circuit implementation techniques have been come up with to prevent active devices from being damaged. One more important issue for handheld applications is that it is imperative to choose a small form factor (height and footprint) external inductor, which can also stand up to 4 A for this particular design. The new trend in small footprint power inductors is to use an iron powder core to keep the inductance constant. This creates a new problem with these types of inductors, whereby the series resistance of the inductor would increase with the frequency, which will increase the inductor AC core losses at switching frequencies of the switching converter. Trade-offs between total harmonic distortion plus noise and boosted voltage levels are also studied.

Characterization of flip chip bonded structure with Cu ABL power bumps

Power distribution in both 2D and 3D integrated circuit (IC) devices becomes one of the key challenges in device scaling, because the on-chip power dissipation becomes significantly severe and causes thermal reliability issues. In this study, the process solution to resolve the on-chip power dissipation by improving power distribution was investigated through newly designed power bumps called ABL (advanced bump layer) bumps. Rectangular-shaped Cu ABL bumps were fabricated and bonded on Si substrate using flip chip bonding process. The bump height difference in signal and ABL power bumps, bonding interface, and electrical resistivity of flip chip bonded structure were evaluated. The lowest electrical resistivity of Cu ABL bump system was estimated to be 3.3E−8Ωm. The process feasibility of flip chip bonded structure with Cu ABL bumps has been demonstrated.

Investigation of On-Chip Hot Spot Cooling Using Microchannel Heat Sink

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.

AC-DIMM

With technology scaling, on-chip power dissipation and off-chip memory bandwidth have become significant performance bottlenecks in virtually all computer systems, from mobile devices to supercomputers. An effective way of improving performance in the face of bandwidth and power limitations is to rely on associative memory systems. Recent work on a PCM-based, associative TCAM accelerator shows that associative search capability can reduce both off-chip bandwidth demand and overall system energy. Unfortunately, previously proposed resistive TCAM accelerators have limited flexibility: only a restricted (albeit important) class of applications can benefit from a TCAM accelerator, and the implementation is confined to resistive memory technologies with a high dynamic range ( R High /R Low ), such as PCM. This work proposes AC-DIMM, a flexible, high-performance associative compute engine built on a DDR3-compatible memory module. AC-DIMM addresses the limited flexibility of previous resistive TCAM accelerators by combining two powerful capabilities---associative search and processing in memory. Generality is improved by augmenting a TCAM system with a set of integrated, user programmable microcontrollers that operate directly on search results, and by architecting the system such that key-value pairs can be co-located in the same TCAM row. A new, bit-serial TCAM array is proposed, which enables the system to be implemented using STT-MRAM. AC-DIMM achieves a 4.2X speedup and a 6.5X energy reduction over a conventional RAM-based system on a set of 13 evaluated applications.

Vision for single flux quantum very large scale integrated technology**This technology was exported from the United States in accordance with the USDepartment of Commerce Export Administration Regulations (EAR) for ultimatedestination in the United Kingdom. Diversion contrary to US law prohibited.

Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip powerdissipation. SFQ VLSI is an excellent candidate for high-performance computing and otherapplications requiring extremely high-speed signal processing. Despite this, SFQ technologyhas generally not been accepted for system implementation. We argue that this is due, atleast in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming theuse of tools equivalent to those employed in the semiconductor industry, we estimate thedensity of Josephson junctions, circuit speed, and power dissipation that could be achievedwith SFQ technology. Today, CMOS lithography is at 90–65 nm with about 20 layers.Assuming equivalent technology, aggressively increasing the current density above100 kA cm−2 to achieve junction speeds approximately 1000 GHz, and reducing device footprints by convertingdevice profiles from planar to vertical, one could expect to integrate about 250 M Josephson junctionscm−2 into SFQ digital circuits. This should enable circuit operation with clock frequencies above200 GHz and place approximately 20 K gates within a radius of one clock period. As aresult, complete microprocessors, including integrated memory registers, could befabricated on a single chip.

Reliability of an 1657CCGA (Ceramic Column Grid Array) Package With 95.5SN3.9AG0.6CU Lead-Free Solder Paste on PCBS (Printed Circuit Boards)

In many applications such as computers and telecommunications, the IC chip sizes are very big, the on-chip frequency and power dissipation are very high, and the number of chip I/Os is very large. The CCGA (ceramic column grid array) package developed by IBM is one of the best candidates for housing these kinds of chips. There are two parts in this study. One is to show that the two-parameter Weibull life distribution is adequate for modeling the thermal-fatigue life of lead-free solder joints. This is demonstrated by comparing the two-parameter and three-parameter Weibull distributions with life test data of an 1657-pin CCGA package with the 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu lead-free solder paste on lead-free printed circuit boards under thermal cycling conditions. The other part of this study is to determine the time-history creep strain energy density of the 1657-pin CCGA solder column with two different solder paste materials, namely, 95.5 wt %Sn3.9 wt %Ag0.6 wt %Cu and 63 wt %Sn37 wt %Pb and under three different thermal cycling profiles, namely, 25↔75°C, 0↔100°C, and −25↔125°C. The effects of these solder pastes and temperature conditions on the thermal-fatigue life of the high-lead (10 wt %Sn90 wt %Pb) solder columns of the CCGA package are provided and discussed.

Development of superconductor electronics technology for high-end computing

This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm−2, 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s−1, both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.

Delay insensitive RSFQ circuits with zero static power dissipation

Total power dissipation in RSFQ circuits consists of two parts, dynamic and static. Dynamic power is dissipated in Josephson junctions performing useful logical and data transmission operations. This dissipation is fundamental and proportional to the data rate (at 4 K, of the order of 10/sup -18/ Joule per bit). Static power is dissipated in resistors used by RSFQ circuits to distribute dc bias current between Josephson junctions. This part of dissipation is not intrinsic to RSFQ circuits and in principle can be eliminated. The goal of this work is to show that Delay Insensitive (DI) RSFQ primitives can be modified so that resistors are no longer required in the dc power supply distribution network, so that the on-chip static power dissipation is absent. In this report we present the schematics for such primitives, define the class of circuits that allow resistor-free current distribution network, and formulate the requirements to the design of this network.

Power minimization and technology comparisons for digital free-space optoelectronic interconnections

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSELs) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bit-rate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSELs and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 /spl mu/m down to 0.1 /spl mu/m brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 /spl mu/m CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm/sup 2/ can be achieved in an optimized free-space optical interconnect system using either VCSELs or MQW modulators as its transmitters.

Free-space optical interconnection: A technology comparison of vertical-cavity surface-emitting lasers and multiple-quantum-well modulators

We evaluate current vertical-cavity surface-emitting laser (VCSEL) and multiple-quantum-well (MQW) modulator technologies for low-fanout system applications. Si-CMOS transimpedance receiver circuits are used in the comparison. The aggregate bandwidth per unit area is calculated from the bandwidth and the total on-chip power dissipation. The results indicate that the electrical power dissipation in the receiver circuits dominates at low operating frequencies. At high operating frequencies the receiver gain drops significantly, thus more electrical power is dissipated in the transmitter to provide more optical power to the receiver to satisfy the voltage requirement at the receiver output. In VCSEL based systems, the optical power is generated entirely on-chip. Thus, only VCSELs with low threshold current and low series resistance would be able to provide the same aggregate bandwidth as the MQW modulator based systems.

A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage read channels

A monolithic active equalizer in 2-/spl mu/m CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations. >

Quantum flux parametron (QFP) shift registers clocked by an inductive power distribution network and errorless operation of the QFP

The authors present 4- and 12-b shift registers capable of operating from DC up to 8.56 and 4.24 GHz, respectively. These circuits' total on-chip power dissipation is estimated to be roughly 10 nW. A novel clock current distribution network permits such high clock frequency and such low on-chip power dissipation. The clock is applied as a standing wave and is distributed by inductive division. With this clock current distribution scheme, no power is dissipated along the clock lines. In spite of the circuits' low output amplitude (tens of microvolts) and of the large crosstalk with the clock frequency, the output waveforms are captured in time domain at microwave frequencies. Also, for the 12-b device, 10/sup 15/ error free operations per quantum flux parametron (QFP) are demonstrated. Finally, the 12-b shift register is the largest QFP circuit reported to date; it is composed of 48 QFPs and one DC SQUID.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digitally adjustable resistors in CMOS for high-performance applications

Methods by which CMOS circuits can be adjusted digitally to generate controlled impedances for use in high-performance circuits are described. Since digital signals are the only inputs to these circuits, on-chip DC power dissipation can be reduced, the circuit can be made more robust, and the impedance of the circuit can be adjusted by manipulating the input digital information. A design of a CMOS series terminated line driver is discussed, and the utilization of the controlled impedance in terminating transmission lines on-chip, constant delay lines, and controlled di/dt output buffers is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Several driving configurations with low-voltage input control for a planar power switch

Several flip-flop control configurations for the coplanar CMOS power switch are proposed that lead to a reduction of the on-chip power dissipation and input control voltage. Moreover, the switch becomes less sensitive to tolerances in the capacitive voltage divider controlling the gate of the output transistor. An acceptable tradeoff between chip area consumed by the flip-flop arrangement, reduction of the on-chip power dissipation, and input control voltage is possible. The on-chip low-voltage control circuitry is also described.

Can perforated-sheet bubble devices be scaled down from 2 to 0.2 micron features

This paper assesses the scaling-down possibility, and determines feasible geometries for miniaturizing the perforated-sheet devices, which offer high speed and simple packaging, but must be improved in density and functional versatilities (replication, swapping, editing, etc.). The use of separate control conductors can provide design flexibility, and over-sized gates and permalloy keepers can relax scaling-down constraints (i.e. electromigration and on-chip power dissipation). Miniaturized devices are implemented with thin propagation sheets, and thick but over-sized control conductors plus keepers. Moreover, 0.2μ bubble devices with functional versatilities appear achievable if suitable bubble medium, lithography, and thin films could be provided.

Current accessed magnetic bubble devices: Projections of performance

A critical analysis is made of the current accessed dual conductor perforated sheet magnetic bubble devices introduced by Bobeck, et al. First, the performance of the existing reported devices is considered. It is shown that although the average power dissipation to propagate one bit of data is relatively high, that with proper chip organization, the average on-chip power dissipation can be kept to tolerably low levels. However, certain components such as the nucleator and the bubble stretcher have such high power dissipation that they are expected to lead to local power dissipation problems on the chip. Assuming these local power dissipation problems can be solved, an analysis of the performance shows that these new devices potentially offer substantially higher data rates and substantially shorter access time than can be obtained with field accessed devices. Scaling rules are developed for the various components on current accessed devices. These scaling rules indicate that for most components, power dissipation per unit area will increase in inverse proportion to the circuit period. Power dissipation in the stretcher, on the other hand, increases even more rapidly with decreasing period and in a 1 Mbit device with 4 μm period would consume 80 percent of the on-chip power. Assuming the problems with power dissipation per unit area can be solved, the scaling rules suggest that the current accessed devices will enjoy an increasing performance advantage over field accessed devices as circuit period is reduced and the chip capacity is increased. This is because the data rate of current accessed devices is projected to increase in inverse proportion to circuit period, whereas the data rate of field accessed devices is dependent on the rotating field drivers and expected to remain constant.

A 4-Mbit full-wafer ROM

A 4-Mbit full-wafer MOS ROM on a 3-in silicon wafer has been designed and characterized. A novel cell structure is utilized in the memory, which results in a small cell area, 99µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , with 5-µm design rules. Efficient defect-tolerant technologies including memory-cell duplication and fail-safe operation are incorporated in order to prevent a decrease in fabrication yield which inevitably occurs in wafer-scale integration. The ROM is composed of four 1-Mbit modules. 3760 characters represented by 18 × 16 dot matrices, most of which are Chinese ideographs (KANJI), are stored in each module as mask ROM data. Memory organization is suitably designed for JIS (Japanese Industrial Standard) KANJI Code and the matrix size. A character is accessed in 12 µs, and 16-bit-wide data are transferred by an internal counter synchronized with an external 1-MHz clock. Measured on-chip power dissipation is 2 W for a full wafer.