Abstract
Power distribution in both 2D and 3D integrated circuit (IC) devices becomes one of the key challenges in device scaling, because the on-chip power dissipation becomes significantly severe and causes thermal reliability issues. In this study, the process solution to resolve the on-chip power dissipation by improving power distribution was investigated through newly designed power bumps called ABL (advanced bump layer) bumps. Rectangular-shaped Cu ABL bumps were fabricated and bonded on Si substrate using flip chip bonding process. The bump height difference in signal and ABL power bumps, bonding interface, and electrical resistivity of flip chip bonded structure were evaluated. The lowest electrical resistivity of Cu ABL bump system was estimated to be 3.3E−8Ωm. The process feasibility of flip chip bonded structure with Cu ABL bumps has been demonstrated.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
