On-chip Linearization Research Articles

Linearized integrated microwave photonic circuit for filtering and phase shifting

Photonic integration, advanced functionality, reconfigurability, and high radio frequency (RF) performance are key features in integrated microwave photonic systems that are still difficult to achieve simultaneously. In this work, we demonstrate an integrated microwave photonic circuit that can be reconfigured for two distinct RF functions, namely, a tunable notch filter and a phase shifter. We achieved >50 dB high-extinction notch filtering over 6–16 GHz and 2π continuously tunable phase shifting over 12–20 GHz frequencies. At the same time, we implemented an on-chip linearization technique to achieve a spurious-free dynamic range of more than 120 dB · Hz4/5 for both functions. Our work combines multi-functionality and linearization in one photonic integrated circuit and paves the way to reconfigurable RF photonic front-ends with very high performance.

Integrated Microwave Photonic Spectral Shaping For Linearization and Spurious-Free Dynamic Range Enhancement

Integrated microwave photonics (MWP) is a fast growing area where high frequency microwave signals are processed in the optical domain, merging key advantages of both microwave photonics and photonic integrated circuits (PICs) technologies including low-loss, reconfigurability, advanced functionality, enhanced stability, and reduced footprint. Plenty of functionalities have been demonstrated in integrated MWP, especially based on spectral shaping technique, where the phase and amplitude of the optical spectrum is precisely tailored by PICs. However, on-chip linearization is lagging behind and has not been investigated deeply. It is crucial and urgent to study on-chip linearization methods, which will lead to advanced integrated MWP systems with large spurious-free dynamic range (SFDR). In this paper, we present two novel techniques for on-chip linearization of microwave photonic links. The first technique is based on line-by-line complex spectral shaping using a series of ring resonators. The second technique relies on spatial separation to achieve parallel spectral shaping in two complementary spatial channels. Both methods are demonstrated in low-loss programmable silicon nitride circuits that can already host a number of advanced functionalities. Our results point to the great potential of integrating advanced functionalities and linearization in the same integrated platform.

Linearized phase modulated microwave photonic link based on integrated ring resonators.

An on-chip linearization method for phase modulated microwave photonic link based on integrated ring resonators is proposed. By properly tailoring the phase and amplitude of optical carrier band and second-order sidebands, the third-order intermodulation distortion (IMD3) components can be suppressed. Theoretical analysis are taken and a proof-of-concept experiment is carried out. Experimental results demonstrate that IMD3 is suppressed by 21.7 dB. When the noise of the link is properly optimized, an SFDR of 112.7 dB·Hz2/3 can be achieved. This opens the possibility of integrating linearization into a functional photonic integrated circuit.

An On-Chip Built-in Linearity Estimation Methodology and Hardware Implementation

An on-chip built-in linearity estimation methodology for a hybrid baseband chain is proposed. The proposed hybrid baseband chain consists of a continuous-time low-pass filter and a discrete-time (DT) finite impulse response filter with a compacted two-stage 3-tap harmonic cancellation (HC). This HC-32 architecture achieves notching at specific programmable frequency points. To estimate the filter linearity, two-tone test signals are injected, and the spectrum power of the DT filter’s output is measured by a power detector. By changing the sampling frequency, the DT filter can switch between the normal operation mode, which allows the two test tones to pass through, or the tone suppression mode, which notches the two test tones and exposes the IM3 tone power. The proposed on-chip linearity estimation methodology is experimentally verified. A comparison between the power measured in the proposed two modes reveals how well is the filter linearity. The proposed baseband chain is fabricated in 130-nm standard CMOS technology, occupying a 0.146-mm2 silicon area. Measurement results shows a suppression of 55 dB on the test tone power.

Hydrogel droplet single-cell processing: DNA purification, handling, release, and on-chip linearization.

The preparation and handling of mammalian single-cell genomic DNA is limited by the complexity bottleneck inherent to performing multi-step, multi-reagent operations in a microfluidic environment. We have developed a method for benchtop preparation of high-molecular weight, intact, single-cell genomes and demonstrate the extraction of long nucleic acid molecules in a microfluidic system. Lymphoblasts are encapsulated inside of alginate microparticles using a droplet microfluidics, and cells are lysed in bulk. The purified genomes are then delivered to and imaged on a dedicated microfluidic device. High-molecular weight DNA is protected from shear and retains its original cellular identity. Using this encapsulation protocol, we were able to extract individual nucleic acid strands on the millimeter scale inside of a microfluidic channel.

An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process.

To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke−. Readout noise under the highest pixel gain condition is 1 e− with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7”, 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

A linearity-enhanced time-domain CMOS thermostat with process-variation calibration.

This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel temperature-sensing cell comprising a simple buffer and a buffer with a thermal-compensation circuit to achieve a linearised delay. Thus, a linearity-enhanced oscillator consisting of these cells can generate an oscillation period with high linearity. To achieve one-point calibration support, an adjustable-gain time stretcher and calibration circuit were adopted for the process-variation calibration. The programmable temperature set point was determined using a reference clock and a second (identical) adjustable-gain time stretcher. A delay-time comparator with a built-in customised hysteresis circuit was used to perform a time comparison to obtain an appropriate response. Based on the proposed design, a thermostat with a small area of 0.067 mm2 was fabricated using a TSMC 0.35-μm 2P4M CMOS process, and a robust resolution of 0.05 °C and dissipation of 25 μW were achieved at a sample rate of 10 samples/s. An inaccuracy of −0.35 °C to 1.35 °C was achieved after one-point calibration at temperatures ranging from −40 °C to 120 °C. Compared with existing thermostats, the proposed thermostat substantially improves the circuit area, accuracy, operating temperature range, and test costs.

A CMOS Envelope-Tracking Transmitter With an On-Chip Common-Gate Voltage Modulation Linearizer

This letter presents a fully integrated CMOS envelope-tracking transmitter with an on-chip common-gate voltage modulation linearizer that achieves an average output power of 26/23.5 dBm with a PAE of 33/28%, an ACLR of -33 / -32.5 dBc at a frequency of 1.9 GHz for 3.84 MHz BW 3.5 dB PAPR WCDMA and 5 MHz BW 7.5 dB PAPR LTE signals in an 0.18-μm CMOS process. The CMOS ET transmitter is integrated with an envelope amplifier, two pairs of saturated power amplifiers, and an on-chip linearizer. The total chip size is 2.5 × 1.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with the input/output on-chip transformers and matching networks.

Reliability analysis of pHEMT power amplifier with an on-chip linearizer

The hot carrier reliability and self-heating of the Al0.3Ga0.7As/In0.25Ga0.75As pHEMT has been examined using mixed-mode simulation. A two-stage power amplifier using 0.15μm InGaAs pHEMT technology with an on-chip linearizer has been designed and fabricated for the evaluation of electrical stress on RF circuit performances. The power amplifier was subjected to high RF input power while doubling the supply voltage for accelerated aging. The experimental data of the amplifier’s output power, power-added efficiency, and linearity show little changes after 10h of continuous RF stress.

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion

A series combining transformer(SCT)-based, watt-level 1.9 GHz linear CMOS power amplifier with an on-chip linearizer is demonstrated. Proposed compact, predistortion-based linearizer is embedded in the two-stage PA to compensate AM-PM distortion of the cascode power stages, and improve ACLR of 3GPP WCDMA uplink signal by 2.6 dB at 28.0 dBm output power. The designed interstage power distributor with one tuning inductor contributes to low-loss power supply for the driver stage and high common-mode stability of the whole PA. Moreover, a newly developed PVT variation- tolerant cascode biasing circuit guarantees highly accurate bias voltages in a wide supply voltage range from 2.5 V to 3.6 V. The test chip demonstrates maximum output power of 28.3 dBm at 1.95 GHz, satisfying 3GPP WCDMA spectrum mask with die area of 5.4 mm2.

PCS/W-CDMA dual-band MMIC power amplifier with a newly proposed linearizing bias circuit

A personal communications service/wide-band code division multiple access (PCS/W-CDMA) dual-band monolithic microwave integrated circuit (MMIC) power amplifier with a single-chip MMIC and a single-path output matching network is demonstrated by adopting a newly proposed on-chip linearizer. The linearizer is composed of the base-emitter diode of an active bias transistor and a capacitor to provide an RF short at the base node of the active bias transistor. The linearizer enhances the linearity of the power amplifier effectively for both PCS and W-CDMA bands with no additional DC power consumption, and has negligible insertion power loss with almost no increase in die area. It improves the input 1-dB gain compression point by 18.5 (20) dB and phase distortion by 6.1/spl deg/ (12.42/spl deg/) at an output power of 28 (28) dBm for the PCS (W-CDMA) band while keeping the base bias voltage of the power amplifier as designed. A PCS and W-CDMA dual-band InGaP heterojunction bipolar transistor MMIC power amplifier with single input and output and no switch for band selection is embodied by implementing the linearizer and by designing the amplifier to have broad-band characteristics. The dual-band power amplifier exhibits an output power of 30 (28.5) dBm, power-added efficiency of 39.5 % (36 %), and adjacent channel power ratio of -46 (-50) dBc at the output power of 28 (28) dBm under 3.4-V operation voltage for PCS (W-CDMA) applications.