On-chip Learning Capability Research Articles

Information Transmission through Biotic-Abiotic Interfaces to Restore or Enhance Human Function.

Advancements in reliable information transfer across biotic-abiotic interfaces have enabled the restoration of lost human function. For example, communication between neuronal cells and electrical devices restores the ability to walk to a tetraplegic patient and vision to patients blinded by retinal disease. These impactful medical achievements are aided by tailored biotic-abiotic interfaces that maximize information transfer fidelity by considering the physical properties of the underlying biological and synthetic components. This Review develops a modular framework to define and describe the engineering of biotic and abiotic components as well as the design of interfaces to facilitate biotic-abiotic information transfer using light or electricity. Delineating the properties of the biotic, interface, and abiotic components that enable communication can serve as a guide for future research in this highly interdisciplinary field. Application of synthetic biology to engineer light-sensitive proteins has facilitated the control of neural signaling and the restoration of rudimentary vision after retinal blindness. Electrophysiological methodologies that use brain-computer interfaces and stimulating implants to bypass spinal column injuries have led to the rehabilitation of limb movement and walking ability. Cellular interfacing methodologies and on-chip learning capability have been made possible by organic transistors that mimic the information processing capacity of neurons. The collaboration of molecular biologists, material scientists, and electrical engineers in the emerging field of biotic-abiotic interfacing will lead to the development of prosthetics capable of responding to thought and experiencing touch sensation via direct integration into the human nervous system. Further interdisciplinary research will improve electrical and optical interfacing technologies for the restoration of vision, offering greater visual acuity and potentially color vision in the near future.

An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning

In this paper, we propose a spike-time based unsupervised learning method using spiking-timing dependent plasticity (STDP). A simplified linear STDP learning rule is proposed for the energy efficient weight updates. To reduce unnecessary computations for the input spike values, a stop mechanism of the forward pass is introduced in the forward pass. In addition, a hardware-friendly input quantization scheme is used to reduce the computational complexities in both the encoding phase and the forward pass. We construct a two-layer fully-connected spiking neuron network (SNN) based on the proposed method. Compared to general rate-based SNNs trained by STDP, the proposed method reduces the complexity of network architecture (an extra inhibitory layer is not needed) and the computations of synaptic weight updates. According to the fixed-point simulation with 9-bit synaptic weights, the proposed SNN with 6144 excitatory neurons achieves 96% of recognition accuracy on MNIST dataset without any supervision. An SNN processor that contains 384 excitatory neurons with on-chip learning capability is designed and implemented with 28 nm CMOS technology based on the proposed low complexity methods. The SNN processor achieves an accuracy of 93% on MNIST dataset. The implementation results show that the SNN processor achieves a throughput of 277.78k FPS with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.50~\mu \text{J}$ </tex-math></inline-formula> /inference energy consuming in inference mode, and a throughput of 211.77k FPS with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.66~\mu \text{J}$ </tex-math></inline-formula> /learning energy consuming in learning mode.

Efficient Neuromorphic Hardware Through Spiking Temporal Online Local Learning

Local learning schemes have shown promising performance in spiking neural networks (SNNs) training and are considered a step toward more biologically plausible learning. Despite many efforts to design high-performance neuromorphic systems, a fast and efficient on-chip training algorithm is still missing, which limits the deployment of neuromorphic systems in many real-time applications. This work proposes a scalable, fast, and efficient spiking neuromorphic hardware system with on-chip local learning capability. We introduce an effective hardware-friendly local training algorithm compatible with sparse temporal input coding and binary random classification weights. The algorithm is demonstrated to deliver competitive accuracy in different tasks. The proposed digital system explores spike sparsity in communication, parallelism in vector–matrix operations and process-level dataflow, and locality of training errors, which leads to low cost and fast training speed. The system is optimized under various performance metrics. Taking into consideration energy, speed, resources, and accuracy, the proposed method shows around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> efficiency over a recent work with a direct feedback alignment (DFA) method and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5\times $ </tex-math></inline-formula> efficiency over the spike-timing-dependent plasticity (STDP) method. Moreover, our hardware architecture can easily scale up with the network size at a linear rate. Thus, our method has demonstrated great potential for use in various applications, especially those demanding low latency.

Obtaining Fuzzy Membership Function of Clusters With the Memristor Hardware Implementation and On-Chip Learning

In this paper, we introduce a memristor-crossbar based hardware in order to implement the Clustering Fuzzification Algorithm with on-chip learning capability. The proposed Clustering Fuzzification Algorithm (CFA) is able to fuzzify all crisp clusters and obtain the fuzzy membership functions based on the density of the clusters. Fuzzy clustering is a more natural way of clustering than hard clustering, which is more similar to the way of categorizing by the human brain. However, there are various crisp algorithms with different capabilities to deal with different clustering problems. By means of CFA, it is possible to benefit from the diversity of crisp clustering algorithms and the advantages of having fuzzy clusters simultaneously. According to the high computational complexity of CFA, utilizing an analog structure of real-time processing can be beneficial. Recently, implementation of neural networks and fuzzy algorithms on memristive devices has emerged in the machine learning field. In this research, in order to take advantages of the memristor devices as the valuable analog structure, the clustering fuzzification algorithm is adapted with the concepts of processing in the memristor-crossbar structure, and an implementation of the algorithm on the memristor-crossbar structure is introduced. Computer simulations confirmed the precision of the implemented algorithm.

A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning

For embedded, mobile and edge-computing intelligent applications, this brief proposes a low-cost real-time neuromorphic hardware system of spiking Extreme Learning Machine (ELM) equipped with on-chip triplet-based reward-modulated spike-timing-dependent plasticity (R-STDP) learning capability. Our design employs a time-step pipelined dual-core architecture consisting of parallel computing unit arrays to improve processing speed, as well as a trace-assisting learning mechanism and on-the-fly hidden layer weight re-generators to significantly reduce hardware resource costs. Our architecture is scalable to different spiking ELM sizes under different tradeoffs among processing speed, recognition accuracy and resource costs. Tests showed that the on-chip triplet R-STDP learning capability can help to achieve relatively high recognition accuracies on our hardware system. An FPGA prototype with low logic and memory resource consumption was implemented, achieving 93% and 78.5% recognition accuracies on the MNIST and Fashion-MNIST image datasets, respectively, at a speed of 30 frames per second (fps) for inference and 22.5 fps for on-chip learning.

Memristor Crossbar-Based Hardware Implementation of Type-2 Fuzzy Membership Function and On-Chip Learning

Utilizing fuzzy techniques, especially fuzzy type-2, is one of the most widely used methods in machine learning to model uncertainty. In addition to algorithm provision, the hardware implementation capability, and proper performance in real-time applications are other challenges. The use of hardware platforms that have biological similarities and are comparable to human neural systems in terms of implementation volume has always been considered. Memristor is one of the emerging elements for the implementation of fuzzy logic based algorithms. In this element, by providing current and selecting the appropriate direction for the applied current, the resistance of the memristor (memristance) will increase or decrease. Various implementations of type-1 fuzzy systems exist, but no implementation of type-2 fuzzy systems has been done based on memristors. In this paper, memristor-crossbar structures are used to implement type-2 fuzzy membership functions. In the proposed hardware, the membership functions can have any shape and resolution. Our proposed implementation of type-2 fuzzy membership function has the potential to learn (On-Chip learning capability regardless of host system). Besides, the proposed hardware is analog and can be used as a basis in the construction of evolutionary systems. Furthermore, the proposed approach is applied to memristor emulator to demonstrate its correct operation.

Neuro-inspired computing chips

The rapid development of artificial intelligence (AI) demands the rapid development of domain-specific hardware specifically designed for AI applications. Neuro-inspired computing chips integrate a range of features inspired by neurobiological systems and could provide an energy-efficient approach to AI computing workloads. Here, we review the development of neuro-inspired computing chips, including artificial neural network chips and spiking neural network chips. We propose four key metrics for benchmarking neuro-inspired computing chips — computing density, energy efficiency, computing accuracy, and on-chip learning capability — and discuss co-design principles, from the device to the algorithm level, for neuro-inspired computing chips based on non-volatile memory. We also provide a future electronic design automation tool chain and propose a roadmap for the development of large-scale neuro-inspired computing chips. This Review Article examines the development of neuro-inspired computing chips and their key benchmarking metrics, providing a co-design tool chain and proposing a roadmap for future large-scale chips.

An Energy-Quality Scalable STDP Based Sparse Coding Processor With On-Chip Learning Capability.

Two main bottlenecks encountered when implementing energy-efficient spike-timing-dependent plasticity (STDP) based sparse coding, are the complex computation of winner-take-all (WTA) operation and repetitive neuronal operations in the time domain processing. In this article, we present an energy-efficient STDP based sparse coding processor. The low-cost hardware is based on the algorithmic reduction techniques as following: First, the complex WTA operation is simplified based on the prediction of spike emitting neurons. Sparsity based approximation in spatial and temporal domain are also efficiently exploited to remove the redundant neurons with negligible algorithmic accuracy loss. We designed and implemented the hardware of the STDP based sparse coding using 65nm CMOS process. By exploiting input sparsity, theproposed SNN architecture can dynamically trade off algorithmic quality for computation energy (up to 74%) for Natural image (maximum 0.01 RMSE increment) and MNIST (no accuracy loss) applications. In the inference mode of operations, the SNN hardware achieves the throughput of 374 Mpixels/s and 840.2 GSOP/s with the energy-efficiency of 781.52 pJ/pixel and 0.35pJ/SOP.

GeCo: Classification Restricted Boltzmann Machine Hardware for On-Chip Semisupervised Learning and Bayesian Inference.

The probabilistic Bayesian inference of real-time input data is becoming more popular, and the importance of semisupervised learning is growing. We present a classification restricted Boltzmann machine (ClassRBM)-based hardware accelerator with on-chip semisupervised learning and Bayesian inference capability. ClassRBM is a specific type of Markov network that can perform classification tasks and reconstruct its input data. ClassRBM has several advantages in terms of hardware implementation compared to other backpropagation-based neural networks. However, its accuracy is relatively low compared to backpropagation-based learning. To improve the accuracy of ClassRBM, we propose the multi-neuron-per-class (multi-NPC) voting scheme. We also reveal that the contrastive divergence (CD) algorithm, which is commonly used to train RBM, shows poor performance in this multi-NPC ClassRBM. As an alternative, we propose an asymmetric contrastive divergence (ACD) training algorithm that improves the accuracy of multi-NPC ClassRBM. With the ACD learning algorithm, ClassRBM operates in the form of a combination of Markov Chain training and Bayesian inference. The experimental results on a field-programmable gate array (FPGA) board for a Modified National Institute of Standards and Technology data set confirm that the inference accuracy of the proposed ACD algorithm is 5.82% higher for a supervised learning case and 12.78% higher for a 1% labeled semisupervised learning case than the conventional CD algorithm. Also, the GeCo ver.2 hardware implemented on a Xilinx ZCU102 FPGA board was 349.04 times faster than the C simulation on CPU.

A novel adaptive learning algorithm for low-dimensional feature space using memristor-crossbar implementation and on-chip training

Proposing an efficient algorithm with an appropriate hardware implementation has always been an interesting and a rather challenging field of research in Artificial Intelligence (AI). Fuzzy logic is one of the techniques that can be used for accurate and high-speed modeling as well as controlling complex and nonlinear systems. The “defuzzification” process during the test phase as well as the repetitive processes in order to find the optimal parameters during the training phase, lead to some serious limitations in real-time applications and hardware implementation of these algorithms. The proposed algorithm employs Ink Drop Spread (IDS) concept to mimic the functionality of human brain. In this algorithm, learning is based on the distance between training data and the “learning plane”. Unlike previous algorithms, the new one does not need to partition nor the input space neither the calculation of IDS plane features. Besides, the output is obtained without using the optimization methods. The proposed algorithm is a numerical foundation that does not encounter a processing problem and lack of memory in dealing with different datasets consisting of a large number of samples. This algorithm can be efficiently implemented on memristor crossbar/CMOS hardware platform in terms of area and speed. This hardware has the ability to learn and adapt to the environment regardless of a host system (on-chip learning capability). Finally, to verify the performance of the proposed algorithm, it has been compared to ALM, RBF and PNN algorithms which have a similar functionality.

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm

A very large-scale integration (VLSI) recognition system equipped with an on-chip learning capability has been developed for real-time processing applications. This system can work in two functional modes of operation: adaptive K-means learning mode and recognition mode. In the adaptive K-means learning mode, the variance ratio criterion (VRC) has been employed to evaluate the quality of K-means classification results, and the evaluation algorithm has been implemented on the chip. As a result, it has become possible for the system to autonomously determine the optimum number of clusters (K). In the recognition mode, the nearest-neighbor search algorithm is very efficiently carried out by the fully parallel architecture employed in the chip. In both modes of operation, many hardware resources are shared and the functionality is flexibly altered by the system controller designed as a finite-state machine (FSM). The chip is implemented on Altera Cyclone II FPGA with 46K logic cells. Its operating clock is 25 MHz and the processing times for adaptive learning and recognition with 256 64-dimension feature vectors are about 0.42 ms and 4 µs, respectively. Both adaptive K-means learning and recognition functions have been verified by experiments using the image data from the COIL-100 (Columbia University Object Image Library) database.

A multilayer neural network with pulse position modulation

AbstractThe problem of the pulse mode neural network is that the synapse weight is bounded between +1 and −1. In order to enhance the weight range, this paper proposes a new weighting method that is a combination of pulse density modulation and pulse position modulation (PPM). The feasibility of the proposed method is verified by experimental MNN with on‐chip learning. A modified back‐propagation algorithm is used for the on‐chip learning. The experimental results show that the proposed MNN architecture has the ability to handle high‐resolution classifying problems and good on‐chip learning capability. © 2003 Wiley Periodicals, Inc. Syst Comp Jpn, 34(13): 36–46, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.10474

Analog on-chip-learning for active noise canceling

Active noise canceling is demonstrated by analog neuro-chips with on-chip learning capability. The developed neuro-chip faithfully incorporates the error-backpropagation learning rule. Without any digital signal processor the developed system successfully compensated for nonlinear distortion of loudspeakers as well as for acoustic multi-path fading and random noises in real time.

Analog LSI implementation of self-learning neural networks

This paper describes a circuit architecture and analog memory devices suitable for analog neural LSIs with on-chip learning capability. First, the essential performances of analog and digital LSI implementations are compared semi-quantitatively and it is derived that the analog approach is more than several thousands times faster than the digital one for feedback networks. Next, a general analog LSI architecture implementing backpropagation networks, Hopfield networks and deterministic Boltzmann machines is proposed and tested using a prototype LSI with 18 neuron I/Os and 81 synapses. Finally, a practical high-speed, high-resolution and non-volatile analog weight memory circuit is proposed and tested. The weight can be updated with more than 14 bit resolution in 1 MHz and is back-uped to a non-volatile memory with 6 bit precision.

Implementation of multilayer neural network with threshold neurons and its analysis

In this paper, the implementation of new digital architecture for a multilayer neural network (MNN) with on-chip learning is discussed. The advantage of using the digital approach is that it can use state-of-the-art VLSI and ULSI implementation techniques. One of the major hard-ware problems in implementing a neural network is the activating function of the neurons. The proposed MNN uses a simple function as the neuron's activating function to reduce the circuit size. Moreover, the proposed MNN has an on-chip learning capability. As the learning algorithm, a backpropagation algorithm is modified for effective hard-wave implementation. The proposed MNN is implemented on a field-programmable gate array (FPGA) to evaluate the learning performance and circuit size.

Mixed analogue–digital artificial-neural-network architecture with on-chip learning

The authors present a novel artificial-neural-network architecture with on-chip learning capability. The issue of straightforward design-flow integration of an autonomous unit is addressed with a mixed analogue–digital approach, by implementing a charge-based artificial neural network which interacts with digital control and processing units. The circuit architecture and design-flow approach for the case of a Hamming network performing pixel-pattern recognition are described.

Analogue neuro-chip with on-chip learning capability for adaptive nonlinear equalisers

Modular neuro-chip sets with an on-chip learning capability are applied to adaptive nonlinear equalisers for mobile communication receivers. Using a multilayer perceptron with a decision feedback architecture is successful for equalising not only minimum phase channels but also nonminimum phase channels.

Effects of multiplier output offsets on on-chip learning for analog neuro-chips

The effects of multiplier output offsets on on-chip learning are analyzed. Offsets on signal feed-forward multipliers are equivalent to sigmoid biases and do not degrade learning performance. Offsets on multipliers for sigmoid derivatives cause static errors at the outputs, which may be overcome by proper choices of target values. Offsets on weight-adjustment multipliers cause not only output static errors but also weight drifts, which are hard to compensate. Therefore weight-adjustment multipliers are most critical for analog neuro-chips with on-chip learning capability. Simulation results agree well with analytic calculations.

Modular neuro-chip with on-chip learning and adjustable learning parameters

A modular analog neuro-chip with on-chip learning capability is described. Two popular learning algorithms, error back-propagation and Hebbian learning, are incorporated with adjustable learning parameters. This analog neuro-chip has a fully modular structure for easy multi-chip expansion. The numbers of synapses and neurons can be expanded by simple pin-to-pin connections without additional circuits. For effective learning, the learning rate, sigmoid slope, and ratio of Hebbian learning term to error back-propagation term can be controlled externally by digital signals. The chip is fabricated and successfully trained with gray-scale patterns as well as XOR problem.