On-chip Flash Memory Research Articles

On-Demand Remote Software Code Execution Unit Using On-Chip Flash Memory Cloudification for IoT Environment Acceleration

In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program’s computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

MTech POL-20 – universal polarograph for electrochemical analytical methods

The simple version of multyfunctional universal polarograph MTech POL-20 based on microcontroller C8051F350 has been designed. The polarograph has functionalities of potentiostat and galvanostat. The C8051F350 chip is fully integrated, low power, mixed-signal system-on-a-chip microconroller unit. It includes high-speed 8051-compatible core, precision programmable 24.5 MHz internal oscillator, 8 kbytes of on-chip flash memory, 24-bit analog to digital converter with analog multiplexer, two 8-bit current output digital to analog converters and 2.5 V voltage reference. The polarograph controls the potential between the working electrode and the reference electrode in range ±2.5 V. The device has four ranges of measured current with programmed selecting: ±15, ±100, ±500 and ±2500 uA. The device can measure voltammograms under high sweep rate from 0.01 and up to 100 mV/s. The polarograph is equipped with RS232-USB converter based on PL2303 chip for power supply and communication with the computer through USB port. Computer program on Visual Basic 5.0 language for operating with potentiostat has been developed. This software allow to measure and visualize voltamperograms, chronopotentiograms and chronoamperograms. For reduction of influence of electromagnetic noise and improvement signal/noise ratio the program makes digital processing of measured polarograms by Savitzky-Golay filter. Potentiostat-galvanostat MTech POL-20 has been successfully tested on model systems using resistive electrochemical equivalents. Also, the polarograph was successfully tested on determination of Pb(II) by anodic stripping voltammetry method. The device is suitable for the main electrochemical measuring techniques and well-known analysis methods: potentiometry and potentiometric titration, coulometry and coulometric titration, voltammetry with different types of potential sweep – linear, normal pulse, differential pulse and square-wave. Keywords : polarograph, potentiostat, galvanostat, microcontroller C8051F350, voltammetry, potentiometry.

Multyfunctional device for electrochemical analytical methods

The simple version of multyfunctional potentiostat-galvanostat MTech PG-410 based on microcontroller C8051F410 has been designed. The C8051F410 chip is fully integrated, low power, mixed-signal system-on-a-chip microconroller unit. It includes high-speed 8051-compatible core, precision programmable 24.5 MHz internal oscillator, 32 kbytes of on-chip flash memory, 12-bit 200 ksps analog to digital converter with analog multiplexer, two 12-bit current output digital to analog converters and 2.2 V voltage reference. The potentiostat-galvanostat controls the potential between the working electrode and the reference electrode in range ±2 V. The potentiostat-galvanostat has three ranges of measured current with manual selecting: ±0.5, ±2 and ±10 mA. The device can measure voltammograms under high sweep rate up to 4 000 mV/s. The device is equipped with RS232-USB converter based on PL2303 chip for power supply and communication with the computer through USB port. Computer program on Visual Basic 5.0 language for operating with potentiostat has been developed. This software allow to measure and visualize voltamperograms, chronopotentiograms, chronoamperograms, potentiometric and coulometric titration curves. For reduction of influence of electromagnetic noise and improvement signal/noise ratio the program makes digital processing of measured polarograms by Savitzky-Golay filter. Potentiostat-galvanostat MTech PG-410 has been successfully tested on model systems using resistive electrochemical equivalents. Also, the main measuring techniques embedded in the device were tested using well-known analysis methods: potentiometric titration of dichromate with Mohr's salt, coulometric titration of thiosulfate with electro-generated iodine and cyclic voltammetry of ferrocyanide/ferricyanide redox couple. Keywords : potentiostat, galvanostat, microcontroller C8051F410, voltammetry, potentiometry.

Area efficient remote code execution platform with on-demand instruction manager for cloud-connected code executable IoT devices

An energy-area efficient cloud-connected software execution architecture in IoT sensor processor is proposed. A remotely installed sensor device such as an environmental activity monitor is commonly implemented using the conventional embedded processor only providing the fixed services, which includes statically compiled embedded software in on-chip flash memory. Instead of conventional on-chip flash memory for an instruction code area, we adopt an virtually mapped internal memory concept to realize cloud-connected software execution, in where the remote storage area via the IoT platform is indirectly mapped onto the physical address space of the instruction memory using a dynamic address translation technique. The proposed cloud-connected architecture of the system enables on-demand code execution for the instructions, which are fetched from the cloud-side remote storage area in the runtime, instead of using a directly-connected on-chip instruction bus. The proposed storage-less approach may be adopted to reduce the high access current and large chip area overhead by eliminating the on-chip code flash memory. To reduce the access current overhead in order to retrieve the requested instruction, a small-sized RAM scratch pad is adopted for retaining the hot-spot instruction code and early filled with pre-estimated instruction sector. The experimental results show that the proposed technique reduces the energy consumption and packet delay of an IoT device for executing the remote embedded software, as well as the reduced chip area by realizing a storage-less sensor architecture.

Efficient Remote Software Management Method based on Dynamic Address Translation for IoT Software Execution Platform in Wireless Sensor Network

Background/Objectives: In this paper, an efficient remote code execution technique is proposed to implement a storage-less sensor in the Internet-of-Things (IoT) paradigm. Methods/Statistical Analysis: To realize a flexible code update mechanism and to optimize the use of an IoT device in terms of utilizing its various functions, we adopt the concept of remote on-demand code execution (ROCE) to implement a storage-less sensor. Findings: Instead of using a conventional on-chip flash memory for an instruction code, an instruction memory is used wherein the remote storage area based on the IoT platform is virtually mapped onto the address space of the instruction memory using a dynamic address translation technique. The proposed storage-less approach using the remote resource as a virtual code space may be adopted to reduce the high access current and chip area overhead of an on-chip code flash memory. Application/Improvements: The proposed technique reduces the energy consumption and the packet delay of an IoT device for executing the remote embedded software, as well as realizes a storage-less sensor architecture.

Low-Power Code Memory Integrity Verification Using Background Cyclic Redundancy Check Calculator Based on Binary Code Inversion Method

The integrity verification of on-chip flash memory data as code memory is becoming important in microcontroller-based applications such as automotive systems. On-the-fly memory fail-detection requires a fast detection method in the seamless background mode without any interruption of CPU operation and low-power flash access hardware to provide safety-conscious execution of the user-programmed firmware during system operations. In this paper, newly-designed read-path architecture based on the binary inversion techniques is proposed for on-chip flash-embedded microcontrollers. The proposed binary inversion method also enables fail-safe, low-power memory access with zero hardware overhead by embedding the scramble flags on the cyclic redundancy check (CRC) protection code. Time-multiplexed CRC calculation for bit-inversion binary code is automatically executed with the silent background mode during CPU idle time without any CPU wait cost. The implementation result shows that the de-inversion procedure could be achieved with just an additional 1,024 bits CRC data in the case of 64 sectors for 4 KB flash memory by reducing 75% of the area of the previous work. The code memory integrity verification time in the seamless background mode is about 30% of the conventional foreground method. The total average current during the code execution for DhrystoneTM benchmark uses just 15% of the basement.

Built-In Binary Code Inversion Technique for On-Chip Flash Memory Sense Amplifier With Reduced Read Current Consumption

The bit-line sense amplifier (S/A) for on-chip flash memory compares cell current with reference current to identify data that are programmed. The S/A for 0 (erased) cell data consumes a large sink current, which is greater than off-current for 1 (programmed) cell data. This brief proposes a built-in write/read path based on binary inversion methods to reduce the sensing current of S/A. An original binary code is programmed into flash memory with an inverted binary code based on the proposed bit inversion techniques. The de-inversion hardware, which is implemented with small logic gates to restore original binary data, only consumes logic current instead of analog sink current in the S/A. The proposed techniques are evaluated for the DSPStone benchmark and are applied to the modified S/A for ARM Cortex-M3-based microcontroller with 128-kB on-chip flash memory based on a 0.18-um EEPROM technology. The circuit-level simulation result for the DSPStone benchmark shows that a newly implemented chip with the S/A based on the proposed technique consumes approximately less than 22% of the operating power that conventional S/A uses.