On-chip Electrostatic Discharge Research Articles

Low-Capacitance and Fast Turn-on SCR for RF ESD Protection

With the smaller layout area and parasitic capacitance under the same electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) has been used as an effective on-chip ESD protection device in radio-frequency (RF) IC. In this paper, SCR's with the waffle layout structures are studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ultra-wide band (UWB) frequencies. With the reduced parasitic capacitance and capacitance variation, the degradation on UWB RF circuit performance can be minimized. Besides, the fast turn-on design on the low-capacitance SCR without increasing the I/O loading capacitance is investigated and applied to an UWB RF power amplifier (PA). The PA co-designed with SCR in the waffle layout structure has been fabricated. Before ESD stress, the RF performances of the ESD-protected PA are as well as that of the unprotected PA. After ESD stress, the unprotected PA is seriously degraded, whereas the ESD-protected PA still keeps the performances well.

ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage N- and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> , negative-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> , positive-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD,</sub> and negative-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13-mum CMOS process have confirmed that the proposed new ESD protection scheme has high human-body model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low- voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces.

Low-Capacitance SCR With Waffle Layout Structure for On-Chip ESD Protection in RF ICs

The silicon-controlled rectifier (SCR) has been used as an effective on-chip electrostatic discharge (ESD) protection device in CMOS technology due to the highest ESD robustness in nanoscale integrated circuits (ICs). In this study, the SCR realized in a waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance. The waffle layout structure of the SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with a waffle layout structure and its turn-on time has also been investigated in a silicon chip.

Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications

Because of its simple structure and snapback characteristics, the grounded-gate NMOS (GGNMOS) has been widely used as an electrostatic discharge (ESD) protection device. ESD performance of GGNMOS fabricated in the 65 nm CMOS process is investigated, and measurement results for the snapback behaviour, failure current It2, holding voltage, and trigger voltage of such advanced MOS devices are illustrated. The effects of four key GGNMOS parameters, channel length, finger number, drain-to-gate spacing and source-to-gate spacing on the ESD performance, are considered, and optimal MOS structures for robust ESD protection applications are suggested.

ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits

Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for integrated circuits (ICs). ESD protection design for giga-Hz high-speed input/output (I/O) circuits has been one of the key challenges to implement high-speed interface circuits in CMOS technology. Conventional on-chip ESD protection circuits at the I/O pads often cause unacceptable performance degradation to high-speed I/O circuits. Therefore, ESD protection circuits must be designed with minimum negative impact to the high-speed interface circuits and to sustain high enough ESD robustness. In this paper, ESD protection design considerations for high-speed I/O circuits are addressed, and the patents related to on-chip ESD protection designs for high-speed I/O circuits are presented and discussed. Keywords: Electrostatic discharge (ESD), input/output (I/O) interface, low capacitance (low-C), power-rail ESD clamp circuit, LC resonator, LC-tank, impedance cancellation, impedance isolation, impedance matching, distributed ESD protection scheme

TCAD Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications

Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical experience and know-how. A technology computer-aided design (TCAD) methodology aimed to assist in the design and implementation of robust ESD devices is developed and presented. The methodology provides a systematic and practical means for the evaluation and optimization of ESD devices in a simulation environment. Advanced silicon-controlled-rectifier devices are considered to illustrate the approach, and experimental data measured from these devices are also included in support of the TCAD development

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.

Compact modeling of on-chip ESD protection devices using Verilog-A

A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON-resistance under transient high-current conditions.

Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.

On-chip electrostatic discharge protection for CMOS gas sensor systems-on-a-chip (SoC)

An on-chip electrostatic discharge (ESD) protection scheme is demonstrated for an emerging technology of microelectromechanical systems (MEMS)-based embedded sensor (ES) system-on-a-chip (SoC). The ESD protection scheme is implemented using ground-referenced multifinger thyristor-type devices optimized for (1) the input/output (I/O) protection, (2) the power supply clamp, and (3) the internal sensors’ electrodes during the micromachining process. The ESD structure developed demonstrates a leakage current below 10 −10 A, high on-state conductance, and high level of human body model (HBM) immunity.

Native-NMOS-Triggered SCR With Faster Turn-On Speed for Effective ESD Protection in a 0.13-$rm murm m$CMOS Process

In order to quickly discharge the electrostatic discharge (ESD) energy and to efficiently protect the ultrathin gate oxide, a novel native-negative-channel metal oxide semiconductor (NMOS)-triggered silicon-controlled rectifier (NANSCR) is proposed for on-chip ESD protection in a 0.13- $ mu m$ complementary metal oxide semiconductor (CMOS) process with a voltage supply of 1.2 V. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger. A new whole-chip ESD protection scheme realized with the proposed NANSCR devices is also demonstrated with the consideration of pin-to-pin ESD stress. From the experimental results, the trigger voltage, holding voltage, turn-on resistance, turn-on speed, and charged-device-model (CDM) ESD level of NANSCR can be greatly improved, as compared with the traditional low-voltage-triggering SCR (LVTSCR). Under transmission line pulsing (TLP) stress, the gate leakage current of the gate monitor device protected by the proposed NANSCR is monitored after each TLP pulse, whereas the gate leakage current is not obviously increased. Therefore, the ultrathin gate oxide of the input stage can be safely protected by the new proposed NANSCR against ESD stress in the nanoscale CMOS technology.

Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits

An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented. The history and evolution of SCR device used for on-chip ESD protection is introduced. Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported. Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed. The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products.

SCR Device Fabricated With Dummy-Gate Structure to Improve Turn-On Speed for Effective ESD Protection in CMOS Technology

Turn-on speed is the main concern for an on-chip electrostatic discharge (ESD) protection device, especially in the nanoscale CMOS processes with ultrathin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device employing a substrate-triggered technique is proposed to improve the turn-on speed of an SCR device for using in an on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible with general CMOS process, without using an extra mask layer or adding process steps. From the experimental results in a 0.25-/spl mu/m CMOS process with a gate-oxide thickness of /spl sim/50 /spl Aring/, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation structure.

ESD protection design considerations for InGaP/GaAs HBT RF power amplifiers

In order to design a robust electrostatic discharge (ESD) protected RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device vulnerability to ESD events in both active transistors and passive components of the HBT technology is presented in this paper. The results include not only the intrinsic HBT's ESD robustness performance, but also its dependence on device layout, ballast resistor, and process. Acknowledging the ESD constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip ESD protection circuit that has a low loading capacitance of less than 0.1 pF and that does not degrade RF and output power performance is developed for wireless local area network application. A diode triggered Darlington pair is implemented as the ESD protection circuit instead of the traditional diode string. Its operation principle, ESD protection performance, and PA performance are also illustrated in this paper.

A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I—ESD

Electrostatic discharge (ESD) continues to be a semiconductor quality and reliability area of interest as semiconductor components are reduced to smaller dimensions. The combination of scaling, design integration, circuit performance objectives, new applications, and the evolving system environments, ESD robustness will continue to be a technology concern. With the transition from silicon bipolar junction transistor to modern BiCMOS silicon germanium (SiGe) semiconductor technologies, new semiconductor process and integration issues have evolved which influence both device performance and ESD protection. Additionally, the issues of low cost, low power and radio frequency (RF) GHz performance objectives has lead to both revolutionary as well as derivative technologies; these have opened new doors for discovery, development and research in the area of on-chip ESD protection and design. With the growth of interest of ESD in RF technology, new innovations and inventions are occurring at a rapid pace. In this paper, we will provide an introductory review of silicon germanium technology and ESD.

ESDInspector: A New Layout-Level ESD Protection Circuitry Design Verification Tool Using a Smart-Parametric Checking Mechanism

On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-/spl mu/m BiCMOS technology.

Investigation on Device Characteristics of MOSFET Transistor Placed Under Bond Pad for High-Pin-Count SOC Applications

In the system-on-a-chip (SOC) era, chip layouts of integrated circuit (IC) products become more and more compact for cost reduction. To save layout area for SOC chips, on-chip electrostatic discharge (ESD) protection devices or input/output (I/O) transistors placed under bond pads is a good choice. To ensure that this choice is practicable, a test chip with large size NMOS devices placed under bond pads had been fabricated in a 0.35-/spl mu/m 1P4M 3.3-V CMOS process for verification. The bond pads of this test chip had been drawn with different layout patterns on the interlayer metals for two purposes. One is to investigate the efficiency against bonding stress applied on the active devices under the bond pads. The other purpose is to reduce the parasitic capacitance of bond pads for high-speed or high-frequency circuit applications. DC characteristics of these devices placed under bond pads had been measured under three conditions: before wire bonding, after wire bonding, and after thermal reliability stresses. After assembly with wire bond package and thermal reliability stresses, the measured results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied to save layout area of IC products by realizing on-chip ESD protection devices or I/O transistors under the bond pads, especially for the high-pin-count SOC.

Novel and Robust Silicon-Controlled Rectifier (SCR) Based Devices for On-Chip ESD Protection

Silicon-controlled rectifiers (SCRs) are frequently used to build on-chip electrostatic discharge (ESD) protection structures, but SCRs are not sufficiently robust to meet a wide range of ESD requirements in various integrated circuits. In this paper, a novel and robust SCR-based device called the HHLVTSCR is presented. It is demonstrated that HHLVTSCR can exhibit various characteristics useful for ESD solutions. An example is also included to illustrate how HHVLTSCRs can be used to provide ESD protection to a practical application.

Esdextractor: a new technology-independent cad tool for arbitrary esd protection device extraction

The challenges for developing an on-chip electrostatic discharge (ESD) protection circuit layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction, and device count reduction. This paper reports a new technology independent layout extractor called the ESDExtractor, which is capable of extracting arbitrary ESD protection devices and answers the demands for full-chip ESD protection design verification. The general methodology to extract both intentional and parasitic ESD protection devices, the specific algorithms, and implementation methods to enhance ESDExtractor's efficiency are presented. Finally, the capability of the new computer-aided design tool is demonstrated using application examples.

SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes

Turn-on efficiency is the main concern for silicon-controlled rectifier (SCR) devices used as an on-chip electrostatic discharge (ESD) protection circuit, especially in deep sub-quarter-micron CMOS processes with much thinner gate oxide. A novel double-triggered technique is proposed to speed up the turn-on speed of SCR devices for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide in sub-quarter-micron CMOS processes. From the experimental results, the switching voltage and turn-on time of such double-triggered SCR (DT-SCR) device has been confirmed to be significantly reduced by this double-triggered technique.