On-chip Coupler Research Articles

Compact inverse designed vertical coupler with bottom reflector for sub-decibel fiber-to-chip coupling on silicon on insulator platform

Inverse design via topology optimization has led to innovations in integrated photonics and offers a promising way for designing high-efficiency on-chip couplers with a minimal footprint. In this work, we exploit topology optimization to design a compact vertical coupler incorporating a bottom reflector, which achieves sub-decibel coupling efficiency on the 220-nm silicon-on-insulator platform. The final design of the vertical coupler yields a predicted coupling efficiency of −0.35 dB at the wavelength of 1550 nm with a footprint of 14 µm × 14 µm, which is considerably smaller than conventional grating couplers. Its topology-optimized geometry can be realized by applying one full-etch and one 70-nm shallow-etch process and the fabricability is also guaranteed by a minimum feature size around 150 nm. Analysis of the potential fabrication imperfections indicates that the topology-optimized coupler is more resilient to in-plane variations, as the deviation of approximately ±100 nm in the misalignment of the topology-optimized features, ±20 nm in the size of the topology-optimized features, and ±10 nm in shallow etch depth yields an additional 1-dB loss as a penalty at the wavelength of 1550 nm. The proposed vertical coupler can further miniaturize photonic integrated circuits and enable highly-efficient networks between optical fibers and other photonic devices.

D-Band On-Chip Couplers With Multilayered Slow-Wave Unit Cell in Standard CMOS Process

D-Band On-Chip Couplers With Multilayered Slow-Wave Unit Cell in Standard CMOS Process

Large-Scale Reconfigurable Integrated Circuits for Wideband Analog Photonic Computing

Photonic integrated circuits (PICs) have been a research hotspot in recent years. Programmable PICs that have the advantages of versatility and reconfigurability that can realize multiple functions through a common structure have been especially popular. Leveraging on-chip couplers and phase shifters, general-purpose waveguide meshes connected in different topologies can be manipulated at run-time and support a variety of applications. However, current waveguide meshes suffer from relatively a low cell amount and limited bandwidth. Here, we demonstrate a reconfigurable photonic integrated computing chip based on a quadrilateral topology network, where typical analog computing functions, including temporal differentiation, integration, and Hilbert transformation, are implemented with a processing bandwidth of up to 40 GHz. By configuring an optical path and changing the splitting ratio of the optical switches in the network, the functions can be switched and the operation order can be tuned. This approach enables wideband analog computing of large-scale PICs in a cost-effective, ultra-compact architecture.

Efficient Low Threshold Frequency Conversion in AlGaAs-On-Insulator Waveguides

A design study is presented for an efficient, compact and robust device to convert the frequency of single-photons from the near-infrared to the telecom C-band. The material platform aluminum gallium arsenide (AlGaAs)-on-insulator, with its relatively large second-order nonlinearity, is used to create highly confined optical modes. This platform can feasibly incorporate single-photon emitters such as indium arsenide (InAs) on gallium arsenide (GaAs), paving the way towards direct integration of single-photon sources and nonlinear waveguides on the same chip. In this design study, single-pass difference-frequency generation (DFG) producing C-band single-photons is enabled via form birefringent phase-matching between a 930 nm single-photon pump and continuous wave (CW) idler at 2,325 nm. In particular the idler and single-photons are combined with an on-chip directional coupler, and then tapered to a single waveguide where the three modes are phase-matched. The design is studied at a special case, showing high fabrication tolerances, and an internal conversion efficiency up to 41%.

On-Chip Terahertz Demultiplexer and Grating Coupler Based on Reverse Design

On-Chip Terahertz Demultiplexer and Grating Coupler Based on Reverse Design

A Sub-THz Wireless Power Transfer for Non-Contact Wafer-Level Testing

In this paper, a sub-THz wireless power transfer (WPT) interface for non-contact wafer-level testing is proposed. The on-chip sub-THz couplers, which have been designed and analyzed with 3-D EM simulations, could be integrated into the WPT to transfer power through an air media. By using the sub-THz coils, the WPT occupies an extremely small chip size, which is suitable for future wafer-testing applications. In the best power transfer efficiency (PTE) condition of the WPT, the maximum power delivery is limited to 2.5 mW per channel. However, multi-channel sub-THz WPT could be a good solution to provide enough power for testing purposes while remaining high PTE. Simulated on a standard 28-nm CMOS technology, the proposed eight-channel WPT could provide 20 mW power with the PTE of 16%. The layouts of the eight-channel WPT transmitter and receiver occupy only 0.12 mm2, 0.098 mm2, respectively.

A Millimeter-Wave Reconfigurable On-Chip Coupler With Tunable Power-Dividing Ratios in 0.13-$\mu$ m BiCMOS Technology

This paper presents a millimeter-wave (mm-wave) on-chip coupler with tunable power dividing ratios and constant phase response. Composed by two coupled lines, two capacitors and two series-connected varactors, the proposed tunable coupler offers broadband frequency responses for 5G applications. Theoretical analysis for wideband operation is provided. For demonstration, a millimeter-wave tunable coupler is implemented in a standard 0.13-$\mu \text{m}$ SiGe (Bi) CMOS technology and measured through an on-wafer probing system. From 24 to 38 GHz, the proposed tunable coupler shows a power-dividing ratio ranged from 0 to 6.5 dB, while maintaining an in-band return loss of better than 10 dB and output isolation of 20 dB, simultaneously. The phase imbalance is better than ±2.5° with a measured insertion loss of 1.3 dB across the entire tuning range. To the authors' best knowledge, this is the first time that an on-chip coupler with tunable power-dividing ratios is reported operating at mm-wave bands for, particularly, 5G applications.

A Phase-Calibration Method for Vector-Sum Phase Shifters Using a Self-Generated LUT

This paper presents a new self-calibration method for vector-sum phase shifters (PS) to compensate for process variations and achieve reconfigurable operating frequency. The calibration system generates a look-up table for the control voltages of the variable-gain amplifiers of the PS to minimize the rms phase error at a frequency of interest. The calibration system consists of a coupled-line coupler, an amplifier, a power detector (PD), an analog-to-digital converter, and a data processing unit. In this calibration method, first, the amplitudes of IQ vectors are swept and their powers are measured. Then, phase errors are calculated from these power measurements using the cosine formula. Finally, the vector pairs providing the least phase error are chosen for each desired phase shift. The practicality of the proposed system is demonstrated by realizing a self-calibrated $X$ -band 7-b PS fabricated in IHP 0.25- $\mu \text{m}$ SiGe BiCMOS technology, including the on-chip coupler, amplifier, and PD. The calibration system improves the rms phase error by at least 1°, does not degrade the rms gain error, and increases the insertion loss by 1.6 dB. The self-calibrated PS achieves a 2° rms phase error across $X$ -band frequencies. The overall chip size is 2.6 mm2. The power consumption of the PS and the overall system are 110 and 233 mW, respectively. This built-in calibration system mitigates process variation effects, and the performance of the PS can be optimized for any center frequency across $X$ -band.

A Simplified Calibration Methodology for On-Chip Couplers

In this paper, we propose a simplified calibration methodology for on-chip couplers to de-embed the unwanted but unavoidable parasitics introduced by the probing pads as well as the effects originating from redundant feeding lines. The traditional TRL (Thru, Reflect, Line) calibration technique for single-ended two-port device is extended and applied to symmetrical 4-port devices that can be decomposed as the odd- and even-mode equivalent circuits. Accordingly, the TRL calibration standards in the balanced format are designed as well. As a final step, single-ended 4-port S-parameters of device under test (DUT) are reconstructed through its de-embedded odd- and even-mode 2-port S-parameters. To validate the efficacy of our proposed calibration methodology in extracting S-parameters of DUT, models in HFSS, such as a branch-line coupler and a coupled-line coupler with probing pads, and balanced TRL calibration standards are generated. After performing the de-embedding procedures proposed in this paper, the extracted S-parameters agree well with the simulated S-parameters of DUT without adding any pads and feeding lines for measurement.

Wideband Millimeter-Wave On-Chip Quadrature Coupler With Improved In-Band Flatness in 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m SiGe Technology

This letter proposes a compact and broadband quadrature coupler with a center frequency of 55 GHz, which consists of a 90° broadside coupled-line to support the differential signal propagation and two T-type L-C networks to support the common signal propagation. To analyze the proposed coupler, an equivalent circuit model is provided for estimation of the distributed and lumped component values. The measured results of the proposed on-chip quadrature coupler show that the return loss and isolation are greater than 20 dB with a bandwidth of 105%, while the insertion loss is about −0.85 dB. The magnitude imbalances are less than 1 dB within the bandwidth of 56% and the phase differences are with ±1° errors within the bandwidth of 96.9%. The chip size, excluding the test pads, is only $0.31\times0.22$ mm2.

Very high efficiency optical coupler for silicon nanophotonic waveguide and single mode optical fiber.

Integrated optical circuits are poised to open up an array of novel applications. A vibrant field of research has emerged around the monolithic integration of optical components onto the silicon substrates. Typically, single mode optical fibers deliver the external light to the chip, and submicron single-mode waveguides then guide the light on-chip for further processing. For such technology to be viable, it is critically important to be able to efficiently couple light into and out of the chip platform, and between the different components, with low losses. Due to the large volume mismatch between a fiber and silicon waveguide (on the order of 600), it has been extremely challenging to obtain high coupling efficient with large tolerance. To date, demonstrated coupling has been relatively lossy and effective coupling requires impractical alignment of optical components. Here, we propose the use of a high contrast metastructure (HCM) that overcomes these issues, and effectively couples the off-chip, out-of-plane light waves into on-chip, in-plane waveguides. By harnessing the resonance properties of the metastructure, we show that it is possible to spatially confine the incoming free-space light into subwavelength dimensions with a near-unity (up to 98%) efficiency. The underlying coupling mechanism is analyzed and designs for practical on-chip coupler and reflector systems are presented. Furthermore, we explore the two-dimensional HCM as an ultra-compact wavelength multiplexer with superior efficiency (90%).

A Fully Integrated Broadband Sub-mmWave Chip-to-Chip Interconnect

A new type of broadband link enabling extremely high-speed chip-to-chip communication is presented. The link is composed of fully integrated sub-mmWave on-chip traveling wave power couplers and a low-cost planar dielectric waveguide. This structure is based on a differentially driven half-mode substrate integrated waveguide supporting the first higher order hybrid microstrip mode. The cross-sectional width of the coupler structure is tapered in the direction of wave propagation to increase the coupling efficiency and maintain a large coupling bandwidth while minimizing its on-die size. A rectangular dielectric waveguide, constructed from Rogers Corporation R3006 material, is codesigned with the on-chip coupler structure to minimize coupling loss. The coupling structure achieves an average insertion loss of 4.8 dB from 220 to 270 GHz, with end-to-end link measurements presented. This system provides a packaging-friendly, cost effective, and high performance planar integration solution for ultrabroadband chip-to-chip communication utilizing millimeter waves.

Periodic Synthesized Transmission Lines With 2-D Routing Capability and Its Applications to Power Divider and Couplers Using Integrated Passive Device Process

A novel periodic synthesized transmission line, comprising periodic unit cells and specially treated corner cells, is proposed and realized using integrated passive device technology. The key innovation is the square unit cell, formed by an asteriated strip overlapped with a capacitive pad. It enables 2-D layout routing since any two of the four arms of the unit cell can serve as the input/output ports. To account for the discontinuity effect at bends, the corner cells are developed independently as a pure lumped T-network to reduce the undesired signal reflection at junctions. Quarter-wavelength synthesized lines are jointed together as miniaturized on-chip couplers. The experimental results demonstrate the compactness of the on-chip components, in addition to their good electrical responses. The uniqueness of the design concept is clearly validated.

A Doherty Power Amplifier With a GaN MMIC for Femtocell Base Stations

A Doherty Power Amplifier (PA) with the proposed GaN MMIC for femtocell base stations is presented. The MMIC was fabricated using a 0.25 μm TriQuint GaN process. An on-chip quadrature coupler based on a lumped magnetic coupler with capacitors was used to reduce the chip size. The MMIC with an area of 2.5 × 2.7 mm2 includes an input matching circuit, a driver transistor, carrier and peak transistors at power stage, and an inter-stage matching network with the quadrature coupler. The Doherty PA with MMIC shows 56.2% power added efficiency (PAE) with a gain of 19.7 dB when the output power is 41.2 dBm for a 2.14 GHz CW signal. For a down link WCDMA signal, the PAE of 39.6% is achieved at an output power of 35.3 dBm. The Doherty PA with the MMIC presented here has a small effective module area of 7 × 15 mm2, which can be readily reduced further.

Millimeter-wave miniaturized hybrid couplers integrated on advanced bicmos technology

In this article, we present the design and the measurement of two hybrid couplers for millimeter-wave applications realized in the BiCMOS9MW 130nm process (ST Microelectronics). The aim is to demonstrate several miniaturization possibilities of a conventional branchline coupler while maintaining a constant 90° phase shift and a low insertion loss over the full 57–66-GHz band. The first miniaturized coupler is composed of meandered transmission lines; the second is a quasi-lumped quadrature coupler with discrete capacitors. The performance of these circuits is compared with the most recent on-chip 60-GHz couplers. We especially demonstrate the possibility to achieve state-of-the-art performance while using miniaturization techniques. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2221–2223, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27079

Fluorescence Intensity Ratio Stereoscopic Transform

A novel approach to 3-D information processing of 2-D cell images is presented, called fluorescence intensity ratio stereoscopic transform (FIRST). Here, we describe its basic principle of image processing and show the results for the ratio of total internal reflection fluorescence (TIRF) to fluorescence intensity. A simple, intuitive transform algorithm would help us to easily obtain a clear stereoscopic image from two 2-D cell images with different fluorescence intensity. For this purpose, nonlinear evanescent-field (EF) imaging of cell-membrane surface and its intracellular structures by using on-chip grating coupler is achieved. This method enabled us to obtain cell images with different signal-to-background ratio and resolution under microfluidic environments. Specifically, we manipulated optic pathway to partially illuminate microscale objects within the microfluidic channel. These findings imply this method will enable selectively to detect optical signals of biomolecular interaction within the cell membrane in a controlled manner. Furthermore, we believe this approach will help to develop an optofluidic sensor for individually detecting dynamic behaviors of intracellular molecules in living cells under microfluidic cell culture environments.

Monolithic Integration of 2-D Multimode Interference Couplers and Silicon Photonic Wires

A new technology using hydrogen annealing and thermal oxidation is proposed to fabricate a very compact 2-D multimode interference coupler monolithically integrated with two-layer silicon photonic wires. Two devices, a 1 × 1 cross-power coupler and a 1 × 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> power splitter, are presented and characterized. The experimental result shows that a 3-dB transmission bandwidth of 1.1 nm, and the on-chip coupler losses of 8.6 dB and 2.84 dB were accomplished for the 1 × 1 cross-power coupler and the 1 × 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> power splitter. This paper demonstrates the possibility of realizing 3-D photonic integration for silicon-on-insulator lightwave circuits.

Design of high-power, high-efficiency 60-GHz MMICs using an improved nonlinear PHEMT model

This work describes the design and nonlinear modeling of two V-band monolithic microwave integrated circuit (MMIC) power amplifiers using a nonlinear high electron mobility transistor (HEMT) model developed specifically for very short gate length pseudomorphic HEMTs (PHEMTs). Both circuits advance the state-of-the-art of V-band power MMIC performance. The first, a single-ended design, produced 293 mW of output power with a record 26% power-added efficiency (PAE) and 9.9 dB of power gain at 62.5 GHz when measured on-wafer. The second MMIC, a balanced design with on-chip input and output Lange couplers for power combining, generated a record 564 mW of output power (27.5 dBm) with 21% PAE and 9.8 dB power gain. The MMIC's are passivated, thinned to 2 mils, and down-biased to 4.5 V for high reliability space applications. These excellent first-pass MMIC results are attributed to the use of an optimized 0.1-//spl mu/m PHEMT cell structure and a design based on millimeter-wave on-wafer device characterization, together with a new and very accurate large signal analytical FET model developed for 0.1-//spl mu/m PHEMTs.