On-chip Communication Architecture Research Articles

Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey

The advancement of manufacturing technologies has enabled the integration of more intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high throughput on-chip communication architecture has become a vital component in today’s SoCs. Diverse technologies such as electrical, wireless, optical, and hybrid are available for on-chip communication with different architectures supporting them. On-chip communication sub-system is shared across all the IPs and continuously used throughout the lifetime of the SoC. Therefore, the security of the on-chip communication is crucial, because exploiting any vulnerability would be a goldmine for an attacker. In this survey, we provide a comprehensive review of threat models, attacks, and countermeasures over diverse on-chip communication technologies as well as sophisticated architectures.

Introduction to the Special Issue on Next-Generation On-Chip and Off-Chip Communication Architectures for Edge, Cloud and HPC

Introduction to the Special Issue on Next-Generation On-Chip and Off-Chip Communication Architectures for Edge, Cloud and HPC

The impact of formulation of cost function in Task Mapping Problem on NoCs using bio-inspired based-metaheuristics

The Task Mapping Problem (TMP) of a Real-Time Application (RTA) onto a Many-/Multi-Processor System-on-a-Chip (MPSoC) with a Network-on-a-Chip (NoC) as on-chip communication architecture can be tackled as an optimization problem to improve desired design features in a static analysis setting. Examples of such features are the system’s compliance with its time requirements. A search-based bio-inspired metaheuristic such as the Genetic Algorithm (GA) can achieve task placement solutions in which all tasks are schedulable. However, the optimization processes are susceptible to the way the cost function is formulated. Additionally, solutions obtained with some of these methods do not consider some of the platform characteristics, such as the number of available virtual channels in the routers, and memory requirements in the processors, rendering their solutions unsuitable for real platforms. Therefore, we propose four objective functions to unify the end-to-end schedulability analysis that considers such platform characteristics. To demonstrate the performance of our objective functions, we conduct a series of experiments mapping the tasks of a benchmark application together with synthetic generated ones onto multiple Network-on-Chip platforms with realistic characteristics. We compare the objective functions during the optimization process using four different metaheuristics, showing that the multi-objective formulation helps the task mapper to achieve solutions that are more suitable for implemented NoC platforms. Although our study focuses on homogeneous NoC-Based MPSoCs, results have generated a better understanding of how the formulation of cost functions impacts the optimization processes for the specific TMP case, considering the Multi-Objective Optimization (MOO) context.

A thermal-sensitive design of a 3D torus-based optical NoC architecture

In order to overcome limitations of traditional electronic interconnects in terms of power efficiency and bandwidth density, optical networks-on-chip (NoC) based on silicon photonics have been proposed as an emerging on-chip communication architecture for chip multiprocessors (CMPs) with large core counts. However, due to thermo-optic effects, wavelength-selective silicon photonic devices such as microresonators suffer from temperature-dependent wavelength shift. In this work, we propose a thermal-sensitive design of a 3D torus-based optical NoC architecture. For the 3D torus-based optical NoC architecture, we propose a hybrid optical-electronic router architecture with a fully-connected 7 × 7 optical switching fabric. Besides, a thermal-sensitive routing algorithm is proposed to optimize the optical power loss in the presence of on-chip temperature variations. Simulation results show that for a set of synthetic traffic patterns, the proposed 3D torus-based optical NoC with the thermal-sensitive routing reduces the average thermal-induced optical power loss by 14.3% and 17% respectively as compared to the matched 3D torus-based optical NoC and the 3D mesh-based optical NoC with the traditional XYZ routing. For a set of real applications, the proposed 3D torus-based optical NoC with the thermal-sensitive routing reduces the worst-case optical power loss by 7.9% and 14.6% respectively as compared to the matched 3D torus-based optical NoC and the 3D mesh-based optical NoC with the traditional XYZ routing.

A Learning-Based Thermal-Sensitive Power Optimization Approach for Optical NoCs

Optical networks-on-chip (NoCs) based on silicon photonics have been proposed as emerging on-chip communication architectures for chip multiprocessors with large core counts. However, due to the thermal sensitivity of optical devices used in optical NoCs, on-chip temperature variations cause significant thermal-induced optical power loss, which would counteract the power advantages of optical NoCs. To tackle this problem, in this work, we propose a learning-based thermal-sensitive power optimization approach for mesh- or torus-based optical NoCs in the presence of temperature variations. The key techniques proposed include an initial device-setting and thermal-tuning mechanism that is a device-level optimization technique, and a learning-based thermal-sensitive adaptive routing algorithm that is a network-level optimization technique. Simulation results of an 8x8 mesh-based optical NoC show that the proposed initial device-setting and thermal-tuning mechanism confines the worst-case thermal-induced optical energy consumption to be on the order of tens of pJ/bit, by avoiding significant thermal-induced optical power loss caused by temperature-dependent wavelength shifts. Besides, it shows that the learning-based thermal-sensitive adaptive routing algorithm is able to find an optimal path with the minimum estimated thermal-induced optical power consumption for each communication pair. The proposed routing has a greater space for optimization, especially for applications with more long-distance traffic.

A Thermal-Aware Power Allocation Method for Optical Network-on-Chip

Optical network on chip (ONoC) is a promising on-chip communication architecture for future many-core systems due to its high performance and energy efficient. ONoC is mostly constructed with microring resonators. However, thermo-optic effect will lead to the drift of the operation point and ultimately have a serious impact on the signal-to-noise rate (SNR). In order to solve this problem, a thermal-aware power allocation method is proposed in this paper. Every communication request should be provided with enough power to satisfy the minimum SNR requirement. Time division multiplexing technology is adopted to solve the power allocation conflicts and communication path conflicts in the network. In order to minimize the number of slots satisfying the rated power supply, an optimization model is established and solved. The simulation results indicate that our proposed method can increase the success rate of communication requests from an average of 43% to 100% in four different on-chip thermal distribution scenarios when compared with four communication scenarios without optimization. It also saves 66.7% of the laser power in average compared with the traditional power allocation method.

Towards real-time crops surveillance for disease classification: exploiting parallelism in computer vision

Considering the incessantly increasing economic losses due to plant diseases in the agricultural sector, we have designed a real-time system capable of classifying plant diseases. In this context, we have proposed an image processing algorithm that transforms the image into three colorspaces, which are processed simultaneously. The algorithm executes in a series of intermediate steps, including contrast stretching, feature vector construction, and identification of salient regions. To enable effective execution, we have also proposed the underlying On-Chip communication architecture that allows efficient interconnection between the three digital signal processing cores, each processing its own colorspace. The architecture has been synthesized for 90 nm process, as well as on an FPGA, achieving a post-layout operational frequency of 644 MHz, and an area of 1208.9 µm2 on the die. We demonstrate that our system outperforms few existing works in literature in terms of accuracy and computation time.

Deadlock Free Load Balanced Adaptive Routing for Network on Chip (NoC) Systems

The Network-on-Chip (NoC) systems have emerged in on-chip communication architecture in various fields. To achieve excellent results in Network on Chip (NoC) systems application, the routing must eliminate the deadlock issues from the network. To overcome this issue in the network, in this paper, we propose Deadlock Free Load Balanced Adaptive Routing. In this approach, Oblivious Routing (OR) algorithm is implemented on the channel by using the probability function. The network considers the capacity of the node and tries to maximize the throughput based on the connectivity between the data packets flow and minimize the channel load. A Reconfiguration Protocol is used for the data packets to choose other channel in the network if the deadlock occurs. Simulation results show that this approach reduces the delay and packet loss in the network.

On Efficient Minimization Techniques of Logical Constituents and Sequential Data Transmission for Digital IC

Objectives: In this paper, a systematic analysis is done on existing logical architecture of on-chip data transmission for a digital integrated circuit like System-on-a-Chip (SoC), Network on Chip (NoC), etc. for fast data communications. Analysis: For systematic comparisons, buses are categorized in different topology based on logical architectures and in the different protocol depending on their communication mechanism. The paper illustrates the operation of the arbiter mechanism. The paper present a systematic analysis of the topology and protocols based on sequential data transmission methods, the priority of accession mode, flexibility and compatibility and performance analysis for the cases of different logic structures and clock frequencies. Finding: Multiple buses are suitable to connect maximum number blocks to avoid the overloading effect on a single bus. The Matrix bus seems to be the best solution for attaining high-speed block data communication, but not energy efficient where as share bus is the most energy efficient bus but not suitable for high-speed operation. Several existing On-Chip Communication Architecture (OCBCA) in the literature and compare them according to their structure, advantages, limitations and application criteria to achieve full performance by minimized logical constituent and the different functional blocks using different communication channels and interconnections. Novelty: Comparison among the all existing on-chip interconnection topology, protocols and minimization techniques of logical constituents.

Special issue on on-chip parallel and network-based systems

In order to achieve functionality with low energy speed product, on-chip parallel and network-based system design requires larger device, multi block functions, and energy evaluation schemes. Such systems,which are emerging as the architecture of choice for future high performance processors, require efficient interconnect which are necessary to satisfy the data supply needs of all cores. This special issue attempts to cover new ideas in the design and analysis of on-chip communication technology, architecture, design methods and applications. In what follows, we will give a brief overview of the accepted papers of this Special Issue based on their topics.

A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs

Recent studies have shown that On-Chip Interconnects (OCI) architecture represents one of the most important component that determines the overall performance of future System-on-Chip (SoC). In order to improve the performance of a specific SoC application domain, the OCI architecture must be optimized at design/run time. Different OCI-based architectures have been recently proposed, the most recent ones are fractal-based or self-similar topologies. In this paper, we present a customization approach by adding strategic links targeted to match large application workload. Simulations results show the effectiveness of this method to achieve better performance compared to the basic OCI architectures. Furthermore, fractal based OCIs perform well almost in all traffic patterns because of their attractive properties.

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip

Multiprocessor systems-on-chip show a trend toward integration of tens and hundreds of processor cores on a single chip. With the development of silicon photonics for short-haul optical communication, wavelength division multiplexing (WDM)-based optical networks-on-chip (ONoCs) are emerging on-chip communication architectures that can potentially offer high bandwidth and power efficiency. Thermal sensitivity of photonic devices is one of the main concerns about the on-chip optical interconnects. We systematically modeled thermal effects in optical links in WDM-based ONoCs. Based on the proposed thermal models, we developed OTemp, an optical thermal effect modeling platform for optical links in both WDM-based ONoCs and single-wavelength ONoCs. OTemp can be used to simulate the power consumption as well as optical power loss for optical links under temperature variations. We use case studies to quantitatively analyze the worst-case power consumption for one wavelength in an eight-wavelength WDM-based optical link under different configurations of low-temperature-dependence techniques. Results show that the worst-case power consumption increases dramatically with on-chip temperature variations. Thermal-based adjustment and optimal device settings can help reduce power consumption under temperature variations. Assume that off-chip vertical-cavity surface-emitting lasers are used as the laser source with WDM channel spacing of 1 nm, if we use thermal-based adjustment with guard rings for channel remapping, the worst-case total power consumption is 6.7 pJ/bit under the maximum temperature variation of 60 °C; larger channel spacing would result in a larger worst-case power consumption in this case. If we use thermal-based adjustment without channel remapping, the worst-case total power consumption is around 9.8 pJ/bit under the maximum temperature variation of 60 °C; in this case, the worst-case power consumption would benefit from a larger channel spacing.

SPEED-POWER EXPLORATION OF 2-D INTELLIGENCE NETWORK-ON-CHIP FOR MULTI-CLOCK MULTI-MICROCONTROLLER ON 28NM FPGA (ZYNQ-7000) DESIGN

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at low cost and lower energy consumption. SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The bus arbitration and synchronization of MultiMicrocontroller System-on-Chip (MMSoC) strongly influences the area, power and performance of the entire system as it uses switching. The synchronization is generally done by multi clocking which leads to power consumption. Future MMSoC designs will need novel on-chip communication architectures that can provide scalable and reliable data transport. On-chip network architectures are believed to be the ideal solution to many of today’s SoC interconnection problems. Network-on-Chip (NoC) architectures may adopt design concepts and methodologies from Multi-Processor/Multi-Microcontroller architectures. Nevertheless, silicon implementation of networks requires a different perspective, because network architectures have to deal with the advantages and limitations of the silicon fabric. These characteristics will require new methodologies for both on-chip switch designs as well as routing algorithm designs. We envision that future on-chip systems will be communication-centric, in particular, energy and performance issues in designing the Multi-Processor/Multi-Microcontroller System-on-Chip will become challenging. In our work we have designed a switch-box for MMSoC for bus synchronization. In this paper, we explore several critical aspects in the bus synchronization of MMSoC by using the generic MultiMicrocontroller System-on-Chip architecture as the experimental platform; this paper presents both quantitative and qualitative analysis on bus synchronization for Network-on-Chip (NoC). Commonly, we synchronize data bus only as it is more important over the other buses namely address bus, control bus and status bus. But by synchronizing other buses we can improve the overall performance of the entire Multi-Microcontroller System-on-Chip. New methodologies and solutions are also proposed to achieve better performance and power balance for MMSoCs.

Power and Area Efficiency NoC Router Design for Application-Specific SoC by Using Buffer Merging and Resource Sharing

Network-on-Chip (NoC) is an efficient on-chip communication architecture specifically for System-on-a-Chip (SoC) design. However, the input buffers of a NoC router often take a significant portion of the silicon area and power consumption. Besides, the performance of a NoC is also greatly affected by the buffer size. In this article, a static buffer merging and resource sharing method is proposed for the application-specific SoC minimizing the NoC buffer. When given an application-specific task graph and the dataflow distribution, the proposed method statically merges rarely used buffers and generates the suitable number of input buffers for each router at design timely. The merged buffer is shared by several input directions. The experimental result shows that the buffer can be utilized more effectively after the resource sharing. Based on the synthesized design with TSMC 90nm technology, the proposed method reduces an average of 42.23% area and 35.13% power while providing similar performance.

System-level performance analysis of multiprocessor system-on-chips by combining analytical model and execution time variation

As the impact of the communication architecture on performance grows in a Multiprocessor System-on-Chip (MPSoC) design, the need for performance analysis in the early stage in order to consider various communication architectures is also increasing. While a simulation is commonly performed for performance evaluation of an MPSoC, it often suffers from a lengthy run time as well as poor performance coverage due to limited input stimuli or their ad hoc applications. In this paper, we propose a novel system-level performance analysis method to estimate the performance distribution of an MPSoC. Our approach consists of two techniques: (1) analytical model of on-chip crossbar-based communication architectures and (2) enumeration of task-level execution time variations for a target application. The execution time variation of tasks is efficiently captured by a memory access workload model. Thus, the proposed approach leads to better performance coverage for an MPSoC application in a reasonable computation time than the simulation-based approach. The experimental results validate the accuracy, efficiency, and practical usage of the proposed approach.

Analysis of Mesh Topology of NoC for Blocking and Non-blocking Techniques

Network on Chip is efficient on-chip communication architecture for system on chip architectures. It enables the integration of a large number of computational and storage blocks on a single chip. The router is the basic element of NoC. The router architecture can be used for building a NoC with standard topology with low latency and high speed. In this paper, we implement and analyze a 3x3 mesh network configuration with routers which can support simultaneous routing requests, with blocking and non blocking inputs.

Performance and cost metrics analysis of a 3D NoC topology using network calculus

The packet switching based Network-on-Chip (NoC) is an obvious interconnect design alternative to the shared bus, crossbar or ring based on-chip communication architecture used in System-on-Chips (SoCs). The advent of the three dimensional NoC (3D NoC) architecture attracts added interest as it offers improved performance and shorter global interconnect. In the 3D NoC architecture, topology plays a vital role in determining the performance of the interconnect architecture. The performance and cost metrics of the 3D NoC topology are evaluated by using simulation in general. However, analytical models provide more insights on how the traffic related parameters influence the performance of the topology. In this paper, the traffic related parameters of a 3D NoC topology, namely 3D Recursive Network Topology (3D RNT) are evaluated by using network calculus based methodology and the results of the evaluation are compared against the results produced using simulation.

Efficient hierarchical bus-matrix architecture exploration of processor pool-based MPSoC

Multiprocessor System-on-Chip (MPSoC) systems are evolving towards a processor pool-based architecture that employs hierarchical on-chip networks for inter- and intra-processor pool communication. Since the design space of processor pool-based MPSoCs is extremely wide, the application-specific optimization of on-chip communication architecture is a nontrivial task. This paper presents a systematic methodology for a cascaded bus matrix-based on-chip network design for processor pool-based MPSoCs. Our approach finds sub-optimal architectures in terms of energy consumption and on-chip area while satisfying given performance constraints. The proposed approach allows for independent configurations of processor pools, which leads to better solutions than seen in previous work. Since a simulation is too time-consuming to evaluate the performance of complex on-chip networks, we propose to prune the designs space efficiently by two static analysis techniques to minimize the use of simulations. Thanks to the static analysis techniques, our approach achieves an order of magnitude speed improvement for architecture exploration without performance loss, compared with simulation-based approaches.

A dynamically reconfigurable communication architecture for multicore embedded systems

To deal with the communication bottleneck of multiprocessor systems, several communication architectures have been proposed in the last decade. Yet, none of them has demonstrated the performance of the direct connections between two communicating units. In this paper, we propose dynamically reconfigurable point-to-point (DRP2P) interconnects for setting up direct connection between two communicating units before the communication starts. DRP2P is neither point-to-point (P2P) nor Network-on-Chip (NoC); it stands between these two on-chip communication architectures. It is as fast as P2P and as scalable as NoC. Instead of using routers like in NoC, we utilize partial reconfiguration ability of FPGAs for routing data packets. Furthermore, DRP2P can work both on regular and irregular topologies. The only drawback of our approach is the reconfiguration latency. This drawback is completely hidden when the reconfiguration of the communication links is achieved during the computation times of the cores. DRP2P solves the scalability issue of P2P by setting up on-demand communication-specific links between cores. So, the occupied area and the total power consumption of communication architecture can be reduced significantly. We designed an on-chip self-reconfiguration core, c 2 PCAP so as to achieve DRP2P interconnects as fast as possible. The c 2 PCAP core is designed for Xilinx FPGAs and can partially reconfigure the FPGA at the highest rate proposed by the manufacturer (e.g. up to 400 MB/s for Virtex-4).

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communication locality is poorly supported, and the importance of floorplanning is overlooked. These significantly limit the power efficiency and performance of optical NoCs. In this work, we address these issues and propose a torus-based hierarchical hybrid optical-electronic NoC, called THOE. THOE takes advantage of both electrical and optical routers and interconnects in a hierarchical manner. It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and hybrid optical-electrical routers with a low-power optical switching fabric. Both of the unfolded and folded torus topologies are explored for THOE. Based on a set of real MPSoC applications, we compared THOE with a typical torus-based optical NoC as well as a torus-based electronic NoC in 45nm on a 256-core MPSoC, using a SystemC-based cycle-accurate NoC simulator. Compared with the matched electronic torus-based NoC, THOE achieves 2.46X performance and 1.51X network switching capacity utilization, with 84% less energy consumption. Compared with the optical torus-based NoC, THOE achieves 4.71X performance and 3.05X network switching capacity utilization, while reducing 99% of energy consumption. Besides real MPSoC applications, a uniform traffic pattern is also used to show the average packet delay and network throughput of THOE. Regarding hardware cost, THOE reduces 75% of laser sources and half of optical receivers compared with the optical torus-based NoC.