Special issue on on-chip parallel and network-based systems

Abstract

In order to achieve functionality with low energy speed product, on-chip parallel and network-based system design requires larger device, multi block functions, and energy evaluation schemes. Such systems,which are emerging as the architecture of choice for future high performance processors, require efficient interconnect which are necessary to satisfy the data supply needs of all cores. This special issue attempts to cover new ideas in the design and analysis of on-chip communication technology, architecture, design methods and applications. In what follows, we will give a brief overview of the accepted papers of this Special Issue based on their topics.