On-chip Digitization Research Articles

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References

Resistive random access memory (RRAM)-based compute-in-memory (CIM) has shown great potential for accelerating deep neural network (DNN) inference. However, device characteristics, such as low-resistance values, susceptibility to drift, and single-level cells, may limit the capabilities of RRAM-based CIM. In addition, prior works generally used the off-chip write-verify scheme to tighten RRAM resistance distributions and used off-chip analog-to-digital converter (ADC) references for fine-tuning partial sum quantization. Although off-chip techniques are viable for testing purposes, they may be unsuitable for practical applications. In this work, we present an RRAM-CIM macro to accelerate DNN inference. The chip features: 1) multi-level cell (MLC) RRAM for improving compute performance and density; 2) sparsity-aware input control to leverage the high activation sparsity in DNN models; 3) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift under stress; and 4) on-chip ADC reference generation that provides column-wise tunability and stability with varying temperatures to guarantee the CIFAR-10 accuracy of 85.8% at 120 °C. The design is fabricated in TSMC 40-nm process with embedded RRAM technology and achieves a macro-level peak performance of 97.8 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 44.5 TOPS/W for multiply-and-accumulate (MAC) operations on VGG-8 network with ternary weights.

High resolution monitoring of chemotherapeutic agent potency in cancer cells using a CMOS capacitance biosensor

Monitoring cell viability and proliferation in real-time provides a more comprehensive picture of the changes cells undergo during their lifecycle than can be achieved using traditional end-point assays. Particularly for drug screening applications, high-temporal resolution cell viability data could inform decisions on drug application protocols that might lead to better treatment outcomes. We describe a CMOS biosensor that monitors cell viability through high-resolution capacitance measurements of cell adhesion quality. The system consists of a 3 × 3 mm2 chip with an array of 16 sensors, on-chip digitization, and serial data output that can be interfaced with inexpensive off-the-shelf components. An imaging system was developed to provide ground-truth data of cell coverage concurrently with data recordings. Results showed the sensor's ability to detect single-cell binding events, track cell morphology changes, and monitor cell motility. A chemotherapeutic assay was conducted to examine dose-dependent cytotoxic effects on drug-resistant and drug-sensitive cancer cell lines. Concentrations higher than 5 μM elicited cytotoxic effects on both cell lines, while a dose of 1 μM allowed discrimination of the two cell types. The system demonstrates the use of real-time capacitance measurements as a proof-of-concept tool that has potential to hasten the drug development process.

微型近红外物联网节点的传感器输出数字化应用研究

The rise of the Internet of Things (IOT) spectral analysis technology has driven the development of near infrared spectroscopy sensors toward miniaturization, digitization and intelligence. A specific digitization research on InGaAs spectral sensor was reported to meet the digital and intelligent development of InGaAs focal plane Arrays (FPA). A new compact near infrared spectral node was developed integratedly with digital output spectral sensor circuit using self-developed analog to digital convertor (ADC) chip. The proposed node integrated 202 effective spectral channels with a wavelength range of 900 nm to 1 700 nm and a spectral resolution better than 16 nm. The wavelength accuracy and repeatability was less than 1 nm and 0.3 nm, respectively. The signal to noise ratio (SNR) of node system was about 500:1, and the frame scanning time was about 3 ms. The research results show that the compact IOT spectral node meets the practical application requirements of near infrared spectral analysis, and provides technical supports for the sensor on-chip digitization and IOT near infrared spectral analysis applications.

Multi-GHz Synchronous Waveform Acquisition With Real-Time Pattern-Matching Trigger Generation

A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 μm CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High-above the high threshold, Low-below the low threshold, Middle-between the two thresholds, or “Don't Care”-any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has been measured to be about 1 part per million, RMS.

A CMOS Integrated W-band Passive Imager

This brief presents an integrated W-band passive imager, including a low-noise amplifier, a Dicke switch, a detector, a low-pass filter, a programmable-gain amplifier, and a 10-bit 20-MHz pipeline analog-to-digital converter (ADC). With digital outputs, the imager is ready to be interfaced with a digital signal processor to complete its system implementation. The chip is realized in a 65-nm CMOS technology. The measured average noise-equivalent power and responsivity are 32 fW/√{Hz} and 103 MV/W, respectively, which represents a noise-equivalent temperature difference of 1.0 K with 30-ms integration time. The integrated imager occupies a silicon area of 1.17 mm2 and burns 151 mW of power. To the authors' best knowledge, this is the first time that a millimeter-wave passive imager is integrated with an on-chip ADC to generate digital outputs.

A generic low-noise CMOS readout interface for 64 × 64 imaging array with on-chip ADC

This paper presents a low-noise and high dynamic-range CMOS readout-IC (ROIC) for a 64 × 64 array of opto-electrical sensors. The readout chain comprises a pixel preamplifier array, correlated-double-sampling based switched-capacitor gain blocks, class-AB output buffer for driving off-chip loads and a 12-bit pipeline ADC for on-chip digitization. The pixel preamplifiers array, occupying an area of 30 μm × 30 μm per pixel, can either be hybridized to a separate IR or UV sensor or can be used as monolithic visible-light active CMOS pixel-array after exposing (by etching the pad) the embedded photodiode under the bonding pads. The ROIC is designed and fabricated in 0.25 μm 1P/5 M CMOS technology with 5 mm × 5 mm of total dimensions. The integrated readout chain, in integrate-then-read mode, demonstrates a dynamic range of 72 dB for electrically emulated sensor currents from 25 pA to 100 nA. It can support a frame rate of 700 fps, with single fully-differential analog as well as 12-bit digital output, at 10 MHz while consuming 17 mW with on-chip biases.

Direct analog-to-microcontroller interfacing

This paper will demonstrate how signals from analog sensors can be directly interfaced to any digital embedded system even though they may not be equipped with an on-chip ADC (Analog-to-Digital Converter), comparator or OP amp (Operational Amplifier). With only two resistors and one capacitor, we will present a solution that allows analog voltages to be measured directly using only a few digital I/O-pins. The digital target system requirements are minimized and limited to only two digital I/O-pins (with tri-state capability). No ADC, comparators, timers or capture modules are necessary. The extremely modest hardware requirements make it a suitable solution also for CPLDs/FPGAs (Complex Programmable Logic devices/Field Programmable Gate Arrays). Since this solution will allow even the simplest embedded system to be interfaced to analog voltage sensors, it has the potential of reducing design costs considerably. The proposed design is for DC or low-frequency signals and compared to other similar solution, this design needs no embedded analog blocks at all.

70-GHz Effective Sampling Time-Base On-Chip Oscilloscope in CMOS

This paper examines a time-base measurement system for on-chip digitization. Undersampling, combined with single-path time-domain amplification and processing, is used to perform the embedded measurement in a time-efficient manner. The proposed system relies on simple circuit components while performing high-speed measurements. Additionally, ease of calibration with minimal silicon area overhead renders the system attractive from a design-for-test perspective. The circuit was implemented in a 0.18-mum standard digital CMOS process using a single 1.8-V supply. On-chip interconnect crosstalk generation with variable strength is included on chip for characterization, and successfully measured using the prototype chip. An effective 70-GHz sampling rate is experimentally obtained from the implemented on-chip oscilloscope, with a voltage resolution of 4 mV. The estimated static power dissipation is ~3.5 mW, with a total active area of 0.45 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> taken up by the associated test and calibration vehicles.

Gigahertz waveform sampling and digitization circuit design and implementation

A series of multichannel transient waveform digitization integrated circuits with up to 5 GHz sample rates and parallel 10-bit digitization have been designed, tested, and fabricated in large quantities. The current CMOS circuit uses four arrays of 128 fast switched capacitors per channel to record four parallel analog transient inputs. High-speed sample clock generation is provided by an analogically adjustable asynchronous active delay line that uses look-ahead to generate 128 multi-GHz four-way interleaved clocks without the need for external high-speed clocking. After transient capture, each channel is fed into 128 parallel 10-bit analog to digital converters for fast, channel-parallel digitization, followed by digital readout. The fast triggering and waveform capture, channel-parallel digitization and convenient word-parallel digital readout results in a responsive and low dead-time system. Acquisition sample rates range from /spl sim/50 kHz to /spl sim/3 GHz. Analog input bandwidth was measured to be /spl sim/350 MHz. Temporal noise is typically equivalent to /spl sim/1 mV root mean square (rms) for a signal-to-noise ratio of /spl sim/2500:1 rms. Fixed-pattern spatial noise, after on-chip digitization, is equivalent to /spl sim/5 mV rms. Current design directions are intended improve on this technology with sample rates in excess of 10 GHz and an analog bandwidth exceeding 1 GHz.