Omega Network Research Articles

Modelling Hadamard Haar transform algorithm for omega connected multiprocessors

Hadamard Haar transform has emphasized the research attention for its application in spectral analysis, bandwidth compression and digital filter design. In this paper, modelling of Hadamard Haar transform has been developed for multistage interconnection network (MIN)-based architecture. The signal flow graph of the existing algorithm has been analysed. The flow graph has been mapped for possible implementation on Omega connected multiprocessor. A modified computational distribution has been suggested for improved efficiency in parallel domain. The modified transform has been modelled for Omega network. The performance comparison has been carried out between original and modified algorithm. The modelling results are compared with the results obtained from mapping the algorithm on Shared Bus and and Mesh connected architecture. The results are expressed as closed form formulae.

The performance of the Cedar multistage switching network

While multistage switching networks for vector multiprocessors have been studied extensively, detailed evaluations of their performance are rare. Indeed, analytical models, simulations with pseudosynthetic loads, studies focused on average-value parameters, and measurements of networks disconnected from the machine, all provide limited information. In this paper, instead, we present an in-depth empirical analysis of a multistage switching network in a realistic setting: We use hardware probes to examine the performance of the omega network of the Cedar shared-memory machine executing real applications. The machine is configured with 16 vector processors. The analysis suggests that the performance of multistage switching networks is limited by traffic nonuniformities. We identify two major nonuniformities that degrade Cedar's performance and are likely to slow down other networks too. The first one is the contention caused by the return messages in a vector access as they converge from the memories to one processor port. This traffic convergence penalizes vector reads and, more importantly, causes tree saturation. The second nonuniformity is the uneven contention delays induced by a relatively fair scheme to resolve message collisions. Based on our observations, we argue that intuitive optimizations for multistage switching networks may not be the most cost-effective ones. Instead, we suggest changes to increase the network bandwidth at the root of the traffic convergence tree and to delay traffic convergence up until the final stages of the network.

Wrap-around type switch for ATM

Proposes a new wrap-around type switch structure based on omega networks. Their uniform interconnection pattern and symmetrical structure helps design a so-called wrap-around switch, The new switch deploys a self-routing mechanism between the input and the output ports. Another characteristic of the switch is the packet filters which are located right in front of the switch elements (SEs). This filtering operation greatly reduces the traffic in the switch fabric by allowing the incoming cells to reach their destination ports without going further in the network.

Nonuniform traffic analysis on a class of self-routing networks

The performance of a class of single-path self-routing networks with 2/spl times/2 switching elements has been analysed in several studies with ad hoc models that are applicable only to the specific traffic pattern and network interconnection pattern considered. The paper describes a generic model that can accommodate different nonuniform traffic patterns and network interconnection patterns. It also presents results obtained with this model for several nonuniform traffic patterns on unbuffered and input-buffered banyan, omega and baseline networks.

A family of interconnection networks for nonuniform traffic

New networks, called GLO networks, are constructed by adding bus-like links to omega networks, providing additional capacity between cells on momentarily busy paths. Equivalent pin-count GLO and omega networks offered uniform and nonuniform traffic were simulated. GLO networks exhibited lower latency for nonuniform traffic and light to moderate uniform traffic.

Comparative Evaluation of Hypermesh and Multi-stage Interconnection Networks

In a multicomputer network, the channel bandwidth is greatly constrained by implementation technology. Two important constraints have been identified in the literature, each appropriate for a particular technology: wiring density limits dominate in VLSI and pin-out in multiple-chip implementations. Most existing interconnection networks are categorized as either direct or indirect (multi-stage) topologies, the mesh and binary n-cube being examples of the former category, the omega and banyan networks of the latter. This paper argues that direct networks based on hypergraph topologies have characteristics which make them particularly appropriate for use in future high-performance parallel systems. The authors have recently introduced a regular multidimensional hypergraph network, called the Distributed Crossbar Switch Hypermesh (DCSH), which has topological properties that permit a relaxation of bandwidth constraints, and which has important topological and performance advantages over direct graph networks. This paper compares the DCSH to multi-stage networks, under both VLSI and multiple-chip technological constraints. The results suggest that in both cases, with a realistic model which includes routing delays through intermediate nodes, the DCSH exhibits superior performance across a wide range of traffic loads.

Optimally routing LC permutations on k-extra-stage cube-type networks

It is difficult to partition an arbitrary permutation into a minimum number of groups such that conflict-free paths for all source-destination pairs in each group can be established on an omega network. Based on linear algebra theory, this paper presents an optimal algorithm which solves this problem for the LC class of permutations on a large class of multi-stage networks. This algorithm extends the previous result which deals with the BPC class of permutations on the omega network.

Components and graph automorphisms of standard 2 × 2‐switch banyan networks

The standard networks of this paper are the Omega network of Lawrie and its various equivalent counterparts and another network which corresponds to the inverse CC-banyan (or restricted data manipulator) but is also built from 2 × 2-crossbar switches. We present several characterizations of graphs which determine the linkage of the switches in these networks. For the graph of the Omega network, such a characterization has been given by Kruskal and Snir and by Bermond, Fourneau, and Jean-Marie. Some of the results of this paper are variants of or inspired by the findings of the latter authors. Apart from the banyan property and conditions on the components of certain subgraphs, use is made of variations of the familiar buddy property. The automorphisms of the aforementioned graphs are determined as well. The structure of the standard networks appears to be largely determined by these mappings. © 1996 John Wiley & Sons, Inc.

Fault-tolerant cube graphs and coding theory

Hypercubes, meshes, tori, and Omega networks are well-known interconnection networks for parallel computers. The structure of those graphs can be described in a more general framework called cube graphs. The idea is to assume that every node in a graph with q/sup l/ nodes is represented by a unique string of l symbols over GF(q). The edges are specified by a set of offsets, those are vectors of length l over GF(q), where the two endpoints of an edge are an offset apart. We study techniques for tolerating edge faults in cube graphs that are based on adding redundant edges. The redundant graph has the property that the structure of the original graph can be maintained in the presence of edge faults. Our main contribution is a technique for adding the redundant edges that utilizes constructions of error-correcting codes and generalizes existing ad hoc techniques.

Components and graph automorphisms of standard 2 � 2-switch banyan networks

The standard networks of this paper are the Omega network of Lawrie and its various equivalent counterparts and another network which corresponds to the inverse CC-banyan (or restricted data manipulator) but is also built from 2 x 2-crossbar switches. We present several characterizations of graphs which determine the linkage of the switches in these networks. For the graph of the Omega network, such a characterization has been given by Kruskal and Snir and by Bermond, Fourneau, and Jean-Marie. Some of the results of this paper are variants of or inspired by the findings of the latter authors. Apart from the banyan property and conditions on the components of certain subgraphs, use is made of variations of the familiar buddy property. The automorphisms of the aforementioned graphs are determined as well. The structure of the standard networks appears to be largely determined by these mappings.

Design and implementation of system software for the super database computer SDC‐II

AbstractThe super database computer SDC‐II is a back‐end massively parallel SQL server, designed for superhigh‐speed processing of queries in relational database systems. The experimental system is composed of tightly coupled parallel processing modules, each containing up to seven CPUs, four disks and two data network interfaces, and a highly functional omega network connecting eight such modules.This paper describes first the parallel relational database processing system, and then proposes a query execution model for its efficient realization. The execution model uses four basic primitives (getPage, putPage, getFree and putFree), which are functions. Processing is performed pagewise using these basic operations. GetPage fetches a page from the disk read buffer, followed by getFree to acquire a free page from the free page pool. The results are sent to a disk write buffer with putPage, and putFree frees the page fetched from the read buffer. In other words, the processing progresses with the page moving around the system. The dataflow control for the input/output processes in the secondary memory for the efficient query processing are discussed in detail later. The method for avoiding and recovering from deadlock are described. Finally, the software system implemented on the SDC‐II is considered describing its components and functions. Measurement results for the execution of the TPC‐D benchmark are shown, indicating that efficient operation is realized.

Bypassing omega network for high speed packet switching

A highly regular switching network consisting of several switching stages for output buffering is proposed. Each switching element performs 3/spl times/3 switching and has a tail-spared buffer for each input port. According to the performance evaluation of the proposed switching network based on computer simulation, a packet loss ratio of 10/sup -8/ was obtained for a 1024/spl times/1024 switching network consisting of 15 stages with the Bernoulli traffic source when the size of tail-spared buffer is 8 and the input traffic load is 0.9.

Optical Omega network: a compact implementation technique

We propose a technique for the compact implementation of an optical Omega network. This technique utilizes the concept that both the perfect-shuffle interconnection and the switching stages can be realized by the same procedures, i.e., duplicate, shift, superimpose, and mask. As a result, a single set of optics is sufficient to realize the whole Omega network in a time-multiplexed recursive manner. Optical setups were designed and a proof-of-principle experiment was performed.

Performance of Buffered Multistage Interconnection Networks in a Nonuniform Traffic Environment

Multistage interconnection networks (MIN) are used to connect processors to memories in shared-memory multiprocessor systems. They have also been proposed as switching fabrics in ATM switches in Broadband ISDN networks. A multistage network consists of several stages of switching elements (SE) connected by a permutation function. Since routing conflicts among packets at the SEs cause blocking and reduce the performance of the network, analytical models have been developed and simulation studies carried out for performance evaluation of MINs in the presence of uniform traffic in the network, Buffers are used at SEs to increase the performance of the network, The suitability of two existing models for possible use in the presence of a hot spot is investigated in this paper, Results show that errors from the models are large. In this paper, we propose a new and efficient Markov chain model for performance evaluation of a single-buffered Omega network in the presence of a hot spot. Results obtained from the existing models and the proposed model for the uniform and the hot spot traffic patterns are presented. It is shown that the proposed model is better than existing models in the presence of hot spot traffic, While the existing models produce small errors in the case of low blocking in the network, the errors become prominent with increased blocking. The proposed model produces accurate results in the more general case of a hot spot traffic, whereas the existing models produce accurate results only in the special case of uniform traffic.

On a class of Banyan networks and tandem Banyan switching fabrics

This paper examines the operating characteristics of a class of tandem Banyan switching fabrics (TBSF's) built using bi-delta networks. We use the functional equivalence between bi-delta networks to induce an equivalence between TBSF's. A weaker form of equivalence guaranteeing identical performance under conditions of symmetric traffic is studied, and a sufficient condition for weak equivalence between functionally distinct TBSF's is established. These results hold for a variety of conflict resolution policies (CRP's) in addition to the one studied by Tobagi et al. (see IEEE J. Select. Areas Commun., vol.9, p.1173, 1991). Simulations indicate that a TBSF constructed by cascading omega networks, (or in fact any other TBSF in its weak equivalence class), performs better than the two TBSF's studied by Tobagi et al., and converges rapidly to a theoretical lower bound on the loss rate, in the region of interest. It is also shown that this loss rate is almost independent of the size of such a TBSF in the region of interest.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Optimal realization of any BPC permutation on K-extra-stage Omega networks

An N/spl times/N k-Omega network is obtained by adding k more stages in front of an Omega network. An N-permutation defines a bijection between the set of N sources and the set of N destinations. Such a permutation is said to be admissible to a k-Omega if N conflict-free paths, one for each source-destination pair defined by the permutation, can be established simultaneously. When an N-permutation is not admissible, it is desirable to divide the N pairs into a minimum number of groups (passes) such that the conflict-free paths can be established for the pairs id each group. Raghavendra and Varma solved this problem for BPC (Bit Permutation Complement) permutations on an Omega without extra stage. This paper generalizes their result to a k-Omega where k can be any integer between 0 and n-1. An O(NlgN) algorithm is given which realizes any BPC permutation in a minimum number of passes on a k-Omega (0/spl les/k/spl les/n-1).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

"Hypermeshes": Optical Interconnection Networks for Parallel Computing

A formal model for a class of optical mesh-based interconnection networks called "hypermeshes" is proposed and characterized. Hypermeshes are based on the concept of orthogonal crossbar switches, with N nodes arranged in n-dimensional mesh structure where all nodes aligned along a dimension are interconnected with an optical multichannel switch. The optical multichannel switches can be modeled as hypergraph "hyperedges" which can perform multiple data transfers over their members simultaneously. The hyperedges can be implemented with space division multiplexing (SDM) in the electrical or optical domains or with wavelength division multiplexing (WDM) over a single fiber in the optical domain. The use of WDM over a fiber also reduces the hypermesh "interconnection complexity" to rival that of a 2D mesh. An architectural characterization is performed and the combinatorial properties, including rearrangeability, permutation capability, partitionability, embedding capability, and bisection bandwidth, are characterized. It is shown that every algorithm which can execute conflict-free on an omega network can execute conflict-free on a hypermesh and that every graph which can be embedded into a hypercube with dilation k can be embedded into a hypermesh with dilation ≤ k. Hypermeshes are shown to have high bisection bandwidths, thereby minimizing the time for many common algorithms such as parallel sorting. It is shown that under the constraint of equivalent aggregate bandwidth the hypermeshes are considerably more powerful computational models than meshes, generalized hypercubes, and other orthogonal graphs. Two attractive optical implementations of hypermeshes using optical technology recently advocated in the literature are also proposed.

Nonblocking properties of interconnection switching networks

Self-routing interconnection networks with their low processing-overhead delay and decentralized routing, are an attractive option for switching fabrics in high speed networks. These interconnection networks, however, realize only a subset of all possible input-output permutations in a non-blocking fashion. The non-blocking property of these networks is an extensively studied area in interconnection network theory field and efficient algorithms exist to check if any given permutation is passable by such networks without blocking. One of the most common interconnection network structures is the inverse omega network and is topologically equivalent to the reverse banyan network. The authors show how to check the passability by the inverse omega network of any given connection set and list some of the very general patterns passable by this network. They also show that the concentrate operation passable by the inverse omega network is just a special case of the more general alternate sequence operation that they show as being passable. These non-blocking properties will be useful for cell routing in switches built with blocking networks in parallel or in cascade. >

Multicommodity flows in simple multistage networks

AbstractIn this paper, we consider the integral multicommodity flow problem on directed graphs underlying two classes of multistage interconnection networks. In one direction, we consider three‐stage networks. Using existing results on (g, f)‐factors of bipartite graphs, we show sufficient and necessary conditions for the existence of a solution when the network has at most two secondary switches. In contrast, the problem is shown to be NP‐complete if the network has three or more secondaries. In a second direction, we introduce a recursive class of networks that includes multistage hypercubic networks (such as the omega network, the indirect binary n‐cube, and the generalized cube network) as a proper subset. Networks in the new class may have an arbitrary number of stages. Moreover, each stage may contain identical switches of any arbitrary size. The notion of extrastage networks is extended to the new class, and the problem is shown to have polynomial time solutions on r‐stage networks where r = 3 or where each link has a unit capacity and r ≥ 3. The latter result implies an efficient algorithm for deciding admissible permutations on conventional extrastage hypercubic networks. In contrast, we show that the multicommodity flow problem is NP‐complete on extrastage networks, even if r = 6, each link has an integral capacity ≤ 3, and all flow demands are equal.

Routing and performance of the double tree (DOT) network

The paper deals with the analysis of an irregular multistage interconnection network called the double tree (DOT) network. A dynamic shortest path routing algorithm for the packet switching DOT network is proposed. The DOT network, being an irregular network, can provide biased pairwise service to favoured connections. Its performance under varying degrees of localised communication is analysed. A comparison with the Omega network is also made.