Ohmic Annealing Research Articles

Electron mobility enhancement in n-GaN under Ohmic-metal

We investigated the electron transport properties of n-GaN under an Ohmic-metal. Hall measurement results were compared for n-GaN (A) before Ti-based metal deposition, (B) after Ti-based metal deposition but before annealing, (C) after Ohmic annealing, and (D) after Ohmic-metal removal, where multi-probe-Hall device measurements are required for (C), while the others, (A), (B), and (D), can be characterized by conventional Hall device measurements. The multi-probe-Hall device measurements for (C) elucidated that, under the Ohmic-metal, the electron concentration is increased and the electron mobility is enhanced in comparison with those for the other cases, (A), (B), and (D). The increased electron concentration indicates that high-density doping takes place in the n-GaN by the Ohmic annealing. However, the high-density doping is not observed after the Ohmic-metal removal. Moreover, the electron mobility enhancement under the Ohmic-metal cannot be explained by donor doping with ionized impurity scattering. These suggest that, under the Ohmic-metal, high-density donors are not formed, and high-density polarization doping owing to strain from the Ohmic-metal takes place. From theoretical calculations, we clarified that the increase in the electron density by polarization doping without donors leads to the suppression of ionized impurity scattering and consequently the electron mobility enhancement.

Impact of the Low Temperature Ohmic Contact Process on DC and Forward Gate Bias Stress Operation of GaN HEMT Devices

In AlGaN/GaN high electron mobility transistors (HEMTs), high temperature processes (such as ohmic annealing with >800°C value) could deform the crystal structure and induce trap states within the bulk and surface. Expanded defect densities cause crucial problems, such as threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> ) instability, current collapse, and high leakages. In this work, a low temperature ohmic contact process (630°C, 10 minutes) is adopted with recess etch, and contact resistances <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 0.1\Omega ~\cdot $ </tex-math></inline-formula> mm with low sheet resistances are achieved. The positive impact of this low thermal budget process on surface morphology, DC operation, long-term stability, and forward gate bias stress of the device is studied.

Ultrathin Interfacial Layer and Pre-Gate Annealing to Suppress Virtual Gate Formation in GaN-Based Transistors: The Impact of Trapping and Fluorine Inclusion

In AlGaN/GaN high electron mobility transistors (HEMTs), the long-term operation of the device is adversely affected by threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\text{V}_{\text{th}}}$ </tex-math></inline-formula> ) instability and current collapse. In this letter, using structural and electrical analyses, the impact of trapping and fluorine (F) inclusion on the device operation is scrutinized. It is found that SiNx interfacial layer significantly reduced the formation of defects, during the ohmic annealing process. Moreover, the incorporation of F ions into GaN bulk, during the gate etch process, triggers the virtual gate phenomenon. This effect has also been mitigated via the pre-gate annealing (PGA) process. As a result of these modifications, a stable operation with minimized lag performance has been achieved.

Post-Annealing on the Ohmic Contact and Gate Recess Simultaneously in AlGaN/GaN MIS-Hemt

AlGaN/GaN HEMTs have been widely used in RF power amplifiers and power switching circuits. The primary reasons are because of high electron mobility and high breakdown electric field in GaN materials. Moreover, a 2DEG formed from polarization effects at the AlGaN/GaN heterojunction enables a low channel resistance and thus a low on-resistance. However, devices fabricated with the inherent 2DEG channel are depletion-mode FETs. For practical applications, it prefers an enhancement-mode (E-mode) device with the threshold voltage > 0 V. The common approaches to implement an E-mode device include gate recess, p-GaN layer, and F-ion treatment. The p-GaN layer used to deplete the channel underneath the gate at 0V and induce 2DEG with positive gate bias. But the gate swing voltage is limited due to the gate leakage current. The F-ion treatment under the gate has a reliability issue. The gate recess combined an insulator layer device (MIS-HEMT) is practical for E-mode operation to achieve the high gate voltage swing and low gate leakage current. However, the damage from gate recess and the relatively poor MOS interface between GaN and the insulators are problems to be overcome. Conventional E-mode MIS-HEMT fabrication starts with high-temperature annealing to ohmic contact then gate recess for gate metallization. Second annealing is required to reduce the gate recess damage. In this study, we did not anneal the device for ohmic contact first but anneal the device after the gate recess with suitable conditions to achieve a good ohmic contact and reduce recess damage. By the post-annealing on the ohmic contact and gate recess simultaneously, the interfacial density of state (Dit) of MIS in the E-mode MIS-HEMT was improved with low contact resistance. The epitaxial layers were grown by MOCVD including a ~3900-nm buffer layer, a 325-nm GaN channel layer, a 1-nm AlN spacer layer, a 21.5-nm Al0.25Ga0.75N barrier, and a 4.1-nm in-situ SiN cap layer. First, device isolation was implemented by ICP etching down to the buffer layer. The ohmic contact was made by the deposition of Ti/Al/Ni/Au (25/125/45/55 nm) without annealing. Using ICP to perform gate recess, and then annealed by RTA at 875 °C in an N2 circumstance for 40 s. The gate dielectric SiN was deposited at 300 °C by PECVD, then annealed by RTA at 450 °C for 1 min in an N2 circumstance. Ni/Ti/Al/Ti/Au (30/25/250/25/200 nm) metal stack was used to form gate metal contact. Finally, the devices were passivated by a 200-nm SiN deposited by PECVD. The C-V and I-V characteristics of fabricated devices were measured by the Agilent B1500A and B1505A. The leakage current was reduced in the devices with proposed annealing. Double sweep C-V characteristics at 100-kHz of devices with proposed annealing step show a smaller hysteresis and lower flat band voltage shift than devices with traditional ohmic annealing. Moreover, the frequency dependent C-V measurements show that device with proposed annealing step effectively reduces the dispersion phenomenon. Conductivity method was applied to extract interface trap density as a commonly used analytical method for the III-V materials [3]. The calculated Dit of the device with proposed annealing step shows lower interface trap density than the device with traditional ohmic annealing. The calculated Dit was reduced from 7.1E12 to 4.8E12 eV-1cm-2. As a result, annealing after gate recess can really improve the interface quality and reduce the damage from dry etching, and form good ohmic contact without the extra annealing step. Figure 1

Normally-Off AlGaN/GaN Heterojunction Metal-Insulator-Semiconductor Field-Effect Transistors With Gate-First Process

In this letter, AlGaN/GaN heterojunction metal-insulator-semiconductor field-effect transistors with gate-first process were developed for normally-off operation with p-GaN cap layers and SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> dielectrics. To avoid the effect of the annealing process on the gate, a low-temperature ohmic contact technique was developed at an annealing temperature of about 500 °C for 20 min in N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient. With the assistance of inductively coupled plasma dry etching, a contact resistance of 1.45 Ω · mm and sheet resistance of 1080.1 Ω/□ were obtained in the recessed region. Owing to the inset of the SiNx layer, the threshold voltage of the fabricated device was enhanced to approximately 2 V, and good pinch-off was observed with the gate voltage up to 16 V. Compared with the conventional high-temperature ohmic annealing process, the gate leakage current was suppressed significantly in both reverse and forward directions. Good device performance was confirmed with a maximum channel electron field-effect mobility of 1500 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> .

Improvement of device isolation using field implantation for GaN MOSFETs

Gallium nitride (GaN) metal-oxide-semiconductor field-effect transistors (MOSFETs) with boron field implantation isolation and mesa isolation were fabricated and characterized. The process of boron field implantation was altered and subsequently conducted after performing high-temperature ohmic annealing and gate oxide thermal treatment. Implanted regions with high resistivity were achieved. The circular MOSFET fabricated in the implanted region showed an extremely low current of 6.5 × 10−12 A under a gate voltage value up to 10 V, thus demonstrating that the parasitic MOSFET in the isolation region was eliminated by boron field implantation. The off-state drain current of the rectangular MOSFET with boron field implantation was 5.5 × 10−11 A, which was only one order of magnitude higher than the 6.6 × 10−12 A of the circular device. By contrast, the rectangular MOSFET with mesa isolation presented an off-state drain current of 3.2 × 10−9 A. The field isolation for GaN MOSFETs was achieved by using boron field implantation. The implantation did not reduce the field-effect mobility. The isolation structure of both mesa and implantation did not influence the subthreshold swing, whereas the isolation structure of only the implantation increased the subthreshold swing. The breakdown voltage of the implanted region with 5 μm spacing was up to 901.5 V.

Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature**Project supported by the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260).

In this paper, TiN/AlOx gated AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOS-HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 °C with the contact resistance approximately 1.6 Ω·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlOx gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AlGaN/GaN MOS-HFETs.

Synthesis of titanium nitride for self-aligned gate AlGaN/GaN heterostructure field-effect transistors.

In this study, titanium nitride (TiN) is synthesized using reactive sputtering for a self-aligned gate process. The Schottky barrier height of the TiN on n-GaN is around 0.5 to 0.6 eV and remains virtually constant with varying nitrogen ratios. As compared with the conventional Ni electrode, the TiN electrode presents a lower turn-on voltage, while its reverse leakage current is comparable with that of Ni. The results of annealing evaluation at different temperatures and duration times show that the TiN/W/Au gate stack can withstand the ohmic annealing process at 800°C for 1 or 3 min. Finally, the self-aligned TiN-gated AlGaN/GaN heterostructure field-effect transistors are obtained with good pinch-off characteristics.

High-voltage GaN-on-Si hetero-junction FETs with reduced leakage and current collapse effects using SiNx surface passivation layer deposited by low pressure CVD

We have investigated the effects of surface passivation on off-state leakage current and current collapse effects of high-voltage GaN-on-Si hetero-junction field effect transistors (HFETs) by using low pressure chemical vapor deposition (LPCVD) of silicon nitride (SiNx). In this work, the metal–oxide–semiconductor (MOS) structure-based HFETs are realized on AlGaN/GaN epitaxy grown silicon substrates by metal–organic chemical vapor deposition (MOCVD). For a comparative study, we have fabricated two types of HFETs, standard and modified MOS-HFETs. In the modified MOS-HFETs process, the surface passivation layer of SiNx is deposited by LPCVD after the mesa isolation step, while the gate is deposited and self-aligned in the trench etched in LPCVD-SiNx layer using inductively coupled plasma reactive ion etching (ICP-RIE). The high temperature deposition of LPCVD-SiNx prevents the degradation caused by the ohmic annealing and other process-induced surface damage. Compared to the standard MOS structure, the modified MOS-HFET devices exhibit 10 times lower off-state leakage currents within high voltage range (0–800 V) and significantly alleviated current collapse effects simultaneously.

Fabrication and Performance of InAlN/GaN-on-Si MOSHEMTs with LaAlO3 Gate Dielectric Using Gate-First CMOS Compatible Process at Low Thermal Budget

Introduction Recently, lattice matched InAlN/AlN/GaN-on-silicon integration approach has attracted increasing attention due to the availability of high-quality GaN epiwafers with high throughput epitaxial growth on large area Si substrates for applications in power and RF devices with low power consumption [1-2]. Meanwhile, the development of gate-first process is useful to realize future self-aligned transistor structures. Conventional fabrication of InAlN/GaN high electron mobility transistors (HEMTs) or metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) involves gate-last process where high temperature (>800 oC) annealing is required to form Ti/Al/Ni/Au source and drain ohmic contacts [3]. This is a consequence of traditional gate metallization (e.g., Ni/Au) and gate dielectric not being able to survive such a high ohmic annealing temperature. Therefore, the development of good ohmic contacts with a low thermal annealing budget and thermally stable gate dielectric is required to realize the gate-first process integration for InAlN/GaN HEMTs/MOSHEMTs. In the present work, we report the fabrication and characterization of InAlN/GaN MOSHEMTs using a lift-off free, gate-first CMOS compatible process developed at low thermal budget. Experiment The lattice-matched In0.18Al0.82N/AlN/GaN-on-Si (111) HEMT structure used in this experiment is shown schematically in Fig. 1. The MOSHEMT fabrication using a gate-first process started from mesa isolation followed by 20 nm thick LaAlO3 (LAO) deposition using pulsed laser deposition (PLD) with a substrate temperature of 300 oC. Then, W was sputter deposited followed by gate definition using photolithography and dry etching method. Thereafter, Hf/Al/Ta layer was sputter deposited followed by rapid thermal annealing at 600 oC for 60 s in vacuum to form source and drain ohmic contacts. Results and Discussion The contact resistance and contact resistivity of Hf/Al/Ta ohmic contacts, as analyzed from linear transmission line method (LTLM), are found to ~0.60 Ω·mm and 6.7x10-6 Ω·cm2, respectively. At first, the thermal stability and reliability of the LAO gate dielectric upon 600 oC ohmic anneal in vacuum was optimized under several oxygen partial pressures during PLD. Comparison of capacitance-voltage and reverse gate leakage current characteristics of fabricated devices subject to different oxygen partial pressures in the range from 3.1×10-5 Torr to 5×10-3 Torr are shown in Figs. 2(a) and 2(b), respectively. It is found that LAO deposited under an oxygen partial pressure of 2.7×10-4 Torr exhibits the lowest gate leakage and highest accumulation capacitance, predominantly arisen by an increased dielectric permittivity (k~23.2). Finally, the gate-first CMOS compatible MOSHEMTs were fabricated by choosing the above optimized deposition condition for PLD (2.7×10-4 Torr @ 300 oC) of LAO. Devices having gate dimensions of W/L = 2×50/1 μm, gate-to-source distance of Lgs ~ 2 μm, gate-to-drain distance of Lgd ~ 6 μm, were used for DC output and transfer characterizations. The DC output and transfer characteristics are shown in Figs. 3 (a) and (b), respectively. The MOSHEMTs achieve a saturation drain current (Idsat) of 500 mA/mm at zero gate voltage, threshold voltage (Vth) of -12.6 V, maximum extrinsic transconductance (Gmax) of 44 mS/mm and on-resistance (Ron) of ~ 14 Ω/mm. Conclusion In conclusion, a gate-first CMOS compatible process for InAlN/AlN/GaN-on-Si MOSHEMTs fabrication has been developed. A low thermal budget (600 oC) for ohmic annealing is achieved through the use of Hf/Al/Ta source-drain contacts, thus allowing the fabrication of gate-first CMOS compatible MOSHEMTs using LaAlO3 as the gate dielectric as well as for device passivation purpose. The reasonable DC performance demonstrated (Idsat = 500 mA/mm, Gmax = 44 mS/mm, etc.) for a 1 μm gate length shows promising possibility for gate-first process integration of InAlN/GaN-on-Si MOSHEMTs.

SiNx Prepassivation of AlGaN/GaN High-Electron-Mobility Transistors Using Remote-Mode Plasma-Enhanced Chemical Vapor Deposition

The surface of AlGaN/GaN high-electron-mobility transistors (HEMTs) tends to be easily damaged during device fabrication, especially during high-temperature annealing. In order to resolve this problem, a prepassivation process was developed using remote-mode plasma-enhanced chemical vapor deposition (RPECVD) systems. It is important in the prepassivation process to protect the region under the gate during high-temperature ohmic annealing and utilize a low-damage SiNx etching process to minimize any surface damage. It was observed that the DC characteristics were significantly improved and the current collapse phenomenon was markedly suppressed for AlGaN/GaN HEMTs by employing the prepassivation process proposed in this work in comparison with a conventional process. According to the experimental results, the prepassivation process coupled with a gate field plate successfully suppressed the current collapse phenomenon in AlGaN/GaN HEMTs. RF output power densities of 6.9 W/mm at 2.3 GHz and >8.9 W/mm at 4 GHz were achieved for AlGaN/GaN HEMTs on Si and SiC substrates, respectively.

Ta-based interface ohmic contacts to AlGaN/GaN heterostructures

Al/Ti based metallization is commonly used for ohmic contacts to n-GaN and related compounds. We have previously reported an ohmic contact scheme specially designed for AlGaN/GaN heterostructure field-effect transistors (HFETs) [D. Qiao et al., Appl. Phys. Lett. 74, 2652 (1999)]. This scheme, referred to as the “advancing interface” contact, takes advantage of the interfacial reactions between the metal layers and the AlGaN barrier layer in the HFET structure. These reactions consume a portion of the barrier, thus facilitating carrier tunneling from the source/drain regions to the channel region. The advancing interface approach has led to consistently low contact resistance on Al0.25Ga0.75N/GaN HFETs. There are two drawbacks of the Al/Ti based advancing interface scheme, (i) it requires a capping layer for the ohmic formation annealing since Ti is too reactive and is easily oxidized when annealing is performed in pure N2 or even in forming gas, and (ii) the atomic number of Al and that of Ti are too low to yield efficient backscattered electron emission for e-beam lithographic alignment purposes. In this work, we investigated a Ta based advancing interface contact scheme for the HFET structures. We found that the presence of Ta in this ohmic scheme leads to (1) a specific contact resistivity as low as 5×10−7 Ω cm2, (2) efficient electron emission for e-beam lithographic alignment, and (3) elimination of the capping layer for the ohmic annealing.