Ultrathin Interfacial Layer and Pre-Gate Annealing to Suppress Virtual Gate Formation in GaN-Based Transistors: The Impact of Trapping and Fluorine Inclusion

Abstract

In AlGaN/GaN high electron mobility transistors (HEMTs), the long-term operation of the device is adversely affected by threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\text{V}_{\text{th}}}$ </tex-math></inline-formula> ) instability and current collapse. In this letter, using structural and electrical analyses, the impact of trapping and fluorine (F) inclusion on the device operation is scrutinized. It is found that SiNx interfacial layer significantly reduced the formation of defects, during the ohmic annealing process. Moreover, the incorporation of F ions into GaN bulk, during the gate etch process, triggers the virtual gate phenomenon. This effect has also been mitigated via the pre-gate annealing (PGA) process. As a result of these modifications, a stable operation with minimized lag performance has been achieved.