Offset Compensation Technique Research Articles

A 6-Gb/s PAM-3 Transceiver With Background Time-Varying Offset Sensing and Compensation

Time-varing offset such as transistor aging increases mismatches of differential pairs at PAM-3 transceivers, exacerbating signal integrity. To tackle this issue, this work proposes a time-varying offset sensing and compensation technique for a PAM-3 transceiver. The proposed compensation algorithm continuously monitors the offset by detecting faulty sensing output patterns and generates optimal reference voltage for the single-to-differential amplifier and DFE to cancel out the offset. The proposed 6 Gbps PAM-3 transceiver was fabricated in 65nm CMOS technology. The proposed offset compensation technique improves the worst-case eye-openings by 38% compared to the baseline design.

A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture

Reconfigurability is an important capability that provides flexibility in computing architecture and low-power technique. It is challenging in digital-in-concept for designing smart analog circuits operated on low power. This work presents a low-power, low-noise, and high-speed multistage feed-forward reconfigurable comparator for medium-to-high-speed analog-to-digital converter. A power-efficient reconfigurable comparator design at 180 nm is presented with a new power reduction and offset compensation technique. The proposed dynamic latch-based 2-stage comparator gives an 83.2% power saving compared with a 3-stage comparator. The reduced number of active stages in comparator lowers the load capacitance to the post-amplifier and the power consumption. The 2-stage comparator gives a high slew rate, low power consumption, and better result at a Nyquist rate of 2.4 GS/s as compared with the previous state of the art. We have also proposed the reconfigurable multistage comparator, which gives the features of both 2-/3-stage comparators. We have performed the post-layout simulation to validate the design for process variation and mismatch with proposed circuit and compared with state of the art. Further, the voltage gain is 100 dB with power supply 1.8 V while consuming 523.4 $$\upmu $$ W and 86.15 $$\upmu $$ W for 3-stage and 2-stage comparator, respectively.

An Accurate Online Prediction Model for Kiln Head Temperature Chaotic Time Series

The kiln head temperature (KHT) is a key thermal variable to condition monitoring and stable control of the rotary kiln. In this paper, a hybrid dynamic prediction framework (HDPF) is proposed to realize the accurate online prediction of the KHT chaotic time series of the rotary kiln. Where, in order to response time-delay and time-varying behaviors of the rotary kiln, the phase space reconstruction (PSR) method is used to achieve the high-dimensional dynamic trajectory of the sintering system of the rotary kiln and the local Volterra filter based on the sliding window technique is developed to construct the dynamic relationship from the high-dimensional dynamic trajectory. Furthermore, considering the practical industrial data contains unreliable risk sometimes, each predicted value is corrected by the offset compensation technique as the final output. Based on well-known Mackey-Glass chaotic time series and real-world KHT chaotic time series from the Inner Mongolia branch of Datang International Power Generation Corporation Limited, comparative experiments show that the HDPF has the highest prediction accuracy which means the HDPF can capture the dynamic evolution of the KHT over time and has the strongest robustness for four kinds of noise which means it can be applied in practical industries with noise. Meanwhile, it has low computational complexity which can meet the real-time requirements of the monitor and control. Further, those good performances imply the HDPF is effective not only for the rotary kiln but also for other complex nonlinear systems with the time-delay and time-varying behaviors.

A robust temperature prediction model of shuttle kiln based on ensemble random vector functional link network

In the sintering process for shuttle kiln, the sintering temperature is the most important thermal parameter, which plays a critical role in stable and efficient operation of the production process. However, due to the complex structure of shuttle kiln, this poses a great challenge for accurate and reliable online prediction of sintering temperature. Therefore, in this paper, a novel prediction model based on ensemble random vector functional link network (AB-RRVFLN) is proposed to predict the temperature. First, the mutual information method is proposed to select the optimal variables for prediction model. Then, considering the outlier influence of industrial data, a robust random vector functional link network (RRVFLN) based on the iteratively reweighted least squares is developed to build prediction model. Moreover, AdaBoost strategy is integrated with RRVFLN model to enhance prediction performance. Finally, the model output is further corrected by offset compensation technique. Based on industrial data from shuttle kiln, the application results on sintering temperature prediction demonstrate that the proposed ensemble method achieves better accuracy and shows stronger robustness than other methods.

Review of DC Offset Compensation Techniques for Grid Connected Inverters

<p><strong></strong>Limitations of DC injection into the AC network is an important operational requirement for grid connected photovoltaic systems. There is one way to ensure that this issue needs a power transformer as a connection to the AC network. However, this solution adds cost, volume, mass, and power losses. Ideally there shouldn't be any DC at the output of the inverter, but practically, a small amount of DC current is present. Therefore, in this paper there are techniques for the DC offset elimination are proposed. Some have drawbacks which was treated by another technique. Also there are best solutions for eliminating DC offset as in section 17, and 18 as it explains how to reduce the DC offset in a transformerless operation with reducing the power losses, mass and the cost effect.</p>

A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation

A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of $3.2\,\,V_{\mathrm {pp-d}}$ ( $\pm 1.33~V_{\text {REF}}$ ). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13- $\mu \text{m}$ CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/−1.0 LSB and INL of 2.3/−2.2 LSB.

Enhancement of touch screen sensing based on voltage shifting differential offset compensation

In this paper, we present an offset compensation technique to enhance the performance of differential sensing circuits for capacitive touch screens. Accurate offset cancellation of differential circuits is regarded as a difficult problem, especially when the offset changes depending on the input signals. The proposed technique can improve the touch detection SNR by compensating both the input and output offset voltage of the differential integrator. It pre-stores the differential offset voltage and corrects both the positive and negative outputs by shifting them by the ½ of the pre-stored offset voltage. We implemented the proposed technique in a touch screen driving and sensing chip using 65 nm CMOS process. Experiments with three different sensing circuit techniques show that the proposed technique provides an SNR improvement of up to 11.17 dB over conventional sensing circuits.

A new high-speed low-power and low-offset dynamic comparator with a current-mode offset compensation technique

In this paper a new low-power high-speed offset-compensated dynamic latched comparator is presented. The proposed comparator uses a two-stage charge-steering preamplifier to achieve high pre-amplification voltage gain. Higher input voltage range of the latch stage significantly reduces the delay time of the latch and relaxes the need for high current in the regeneration process which ensures low-power structure. In addition, a new digitally controlled offset cancellation circuit based on the current-steering structure is used to reduce the offset of comparator. Offset voltage reduction in the startup time is the key advantage of the proposed calibration technique which does not require refreshing the offset cancellation process. Post-layout simulation results in 0.18µm standard TSMC CMOS process show that the designed comparator dissipates 135µW of power consumption from a 1.2V supply voltage and has the 1mV accuracy while operating at 1GHz clock frequency. The power and delay time of the proposed comparator are less than about 10% of the new state-of-the-art comparator. Furthermore, from the Monte-Carlo analysis, the standard deviation of the input referred offset voltage in typical process corner and temperature is obtained about 17.53/1.09mV before and after offset cancellation, respectively.

A synchronous analog very front-end in 65 nm CMOS with local fast ToT encoding for pixel detectors at HL-LHC

This work describes the design, in 65 nm CMOS, of a very compact, low power, low threshold synchronous analog front-end for pixel detectors at HL-LHC . Threshold trimming is avoided using offset compensation techniques. Fast ToT encoding is possible, as the comparator can be turned into a Local Oscillator up to several hundreds MHz. Two small prototypes have been submitted and tested; a X-ray irradiation up to 600 Mrad has been performed. Detailed results in terms of gain, noise, ToT and threshold dispersion are presented. This design will be part of the CHIPIX65 demonstrator and of the RD53A chip.

Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments

The upgrade of the silicon pixel sensors for the HL-LHC experiments requires the development of new readout integrated circuits due to unprecedented radiation levels, very high hit rates and increased pixel granularity. The design of a very compact, low power, low threshold analog very front-end in CMOS 65 nm technology is described. It contains a synchronous comparator which uses an offset compensation technique based on storing the offset in output. The latch can be turned into a local oscillator using an asynchronous logic feedback loop to implement a fast time-over-threshold counting. This design has been submitted and the measurement results are presented.

A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration

A subranging analog-to-digital converter (ADC) features high-speed and relatively low-power. The limiting factors of power reduction in subranging ADCs are the resistor ladder and the comparator. We propose an ADC architecture combining a capacitive digital-to-analog convertor and built-in threshold calibration to eliminate the resistor ladder, resulting in a low-power subranging ADC. We also propose a calibration technique comprising of metal-oxide-metal capacitor, MOS switch, and scaling capacitor to reduce the power consumption of the comparator and an offset drift compensation technique to enable precise foreground calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these techniques, and post-layout simulation results demonstrated a power consumption of 7 mW and figure of merit of 51 fJ/conv.-step.

차동 델타 샘플링 기법을 이용한 비냉각형 적외선 검출회로의 설계에 관한 연구

A uncooled infrared ray sensor used in an infrared thermal imaging detector has many advantages. But because the uncooled infrared ray sensor is made by MEMS (micro-electro-mechanical system) process variation of offset is large. In this paper, to solve process variation of offset a ROIC for uncooled infrared ray sensor that has process variation of offset compensation technique using differential delta sampling and reference signal compensation circuit was proposed. As a result of simulation that uses the proposed ROIC, it was possible to acquire compensated output characteristics without process variation of offsets.

An improved low offset latch comparator for high-speed ADCs

This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 200 μV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 μW from a 1.8 V supply while operating in 500 MHz clock frequency.

An Inrush Current Mitigation Technique for the Line-Interactive Uninterruptible Power Supply Systems

Unexpected voltage sags or outages often interrupt the operation of manufacturing processes or even lead to equipment damage. Numerous critical loads rely on the uninterruptible power supply system to uphold the power during these events and maintain the normal operation. As disturbances occur in the utility, the uninterruptible power supply (UPS) should take over the load within 1-5 ms to prevent any interruptions. However, the startup process of the UPS can cause the significant inrush current phenomenon on the load transformer due to magnetic saturation. The inrush current could result in reduced line voltages and even trigger the UPS's overcurrent protection. To prevent the inrush current, this paper proposes a flux offset compensation technique based on the synchronous reference frame (SRF) to regulate the flux of the load transformer. The proposed technique can be integrated with the existing voltage control and the pulse-width modulation (PWM) of the UPS inverter without any additional sensors. The proposed technique can provide a very smooth and timely transition without the risk of inrush current for critical loads under power outages and voltage sags.

A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC

Zero-crossing based switch capacitor circuits have been introduced as alternatives to op-amp based circuits for eased design considerations and improved power efficiency. This work further improves the resolution, power efficiency, and robustness of previous zero-crossing based circuits (ZCBCs) and features a 90 nm CMOS, offset compensated, fully differential, zero-crossing based, 12b, 50 MS/s, pipelined ADC requiring no CMFB. The power consumption is 4.5 mW. The FOM is 88 fJ/step. Fully differential signaling is used to improve power supply rejection and power efficiency. A power efficient chopping offset compensation technique is presented. Reference voltage switching is improved to avoid gate boosted switches. Redundancy is used to reduce output range requirements for increased signal range. Two regenerative latch architectures used for bit decision comparison are analyzed and measured for offset, noise, and speed.

Performance Tradeoffs of Three Novel GMR Contactless Angle Detectors

Three innovative solutions for contactless angle detection are described and compared. They use a giant magnetoresistive (GMR) sensor bridge which detects the direction of the magnetic field of a rotatable magnet placed near the sensor. The three solutions differ in the CMOS Application-Specific Integrated Circuit (ASIC) employed as sensor signal conditioning interface, leading to different cost-performance tradeoffs. The first ASIC is all-analog, being the simplest and cheapest one. The second ASIC is a mixed-mode solution providing a pulse width modulated (PWM) output, and its main innovation is the use of a compact piecewise-linear ADC to compensate for the sensor nonlinearity. This way, linearization and A/D conversion are performed simultaneously, saving power and silicon area. The third ASIC is mostly digital and fully programmable, being the most flexible and accurate (albeit costly) solution. It incorporates as main novelties a new offset compensation technique that shares most of required circuits with the successive-approximation ADC, and a new combinational circuit for linearization. Measurement results for the three implementations are provided, and their performance tradeoffs discussed.

A Frequency Offset Estimation Technique Based on CCK for a WLAN Receiver Design

This paper studies a frequency offset estimation and compensation technique taking advantage of complementary code keying (CCK) in a baseband architecture. The proposed technique can switch between coarse and fine frequency offset estimation subsystems in order to achieve lower estimation errors and lower bit-error rates (BERs). The architecture mainly exploits the specific characteristics of the CCK code set; thus it blindly extracts the frequency offset without any assistance from a training sequence. The proposed technique is very suitable to be employed in a CCK-based WLAN system for the purpose of increasing data transmission rate. Extensive computer simulations show that the proposed technique and its architecture realization exhibit superiority in overall system performance.

On-Panel Output Buffer With Offset Compensation Technique for Data Driver in LTPS Technology

To overcome the offset voltage (VOS) of output buffer due to large variation on characteristics of thin-film transistor (TFT) in low-temperature polysilicon (LTPS) technology, a class-B output buffer with offset compensation circuit for the data driver is presented in this paper. This proposed class-B output buffer can operate at 50-kHz operation frequency with a 2-8-V output swing for extended graphic array (XGA) application, and it has been demonstrated in 3-mum LTPS technology. Using the offset compensation technique, the VOS of output buffer can be controlled within plusmn100 mV under 2-to-8 V signal operation to achieve a high resolution and quality liquid crystal display (LCD) panel

Design of Monolithic Tunable CMOS Band-Pass Filter Using Current Feedback Operational Amplifiers

We propose in this paper a tunable second order band-pass filter based on two CMOS current feedback operational amplifiers (CFOAs). The CFOA includes a novel offset compensation technique. A digital building block is implemented in the proposed band-pass filter to tune its central frequency. An important feature of the adopted tuning procedure is the ability to tune the filter without affecting other characteristics such as gain, phase and quality factor. The band-pass filter topology is validated with a configuration where the central frequency is tuned from 60 MHz to 95 MHz with frequency steps of 5 MHz. Measurements of the offset-compensated CFOA are promising, and simulation results of the CFOA-based band-pass filter using the 0.18 ? m CMOS process confirm our theoretical analysis.

An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs

The input referred offset voltage occurring in the full latch V/sub DD/ biased sense amplifier has been analyzed extensively. The process variations in the matched nMOS and pMOS transistors have been accounted by /spl plusmn/2.5% variation in V/sub T/ and /spl plusmn/5% variation in /spl beta/, from typical values. Effect of various design parameters on the sense amplifier offset has been studied and reported. It has been shown that the rise time of the sense amplifier enable signal (SAEN) has a profound effect on the offset voltage. The slower transition of SAEN signal is proposed to result in high speed as well as low-power consumption in SRAM application. An analytical model has been derived for simplified latch to model the effect of rise time of SAEN signal on offset voltage.