Abstract
Time-varing offset such as transistor aging increases mismatches of differential pairs at PAM-3 transceivers, exacerbating signal integrity. To tackle this issue, this work proposes a time-varying offset sensing and compensation technique for a PAM-3 transceiver. The proposed compensation algorithm continuously monitors the offset by detecting faulty sensing output patterns and generates optimal reference voltage for the single-to-differential amplifier and DFE to cancel out the offset. The proposed 6 Gbps PAM-3 transceiver was fabricated in 65nm CMOS technology. The proposed offset compensation technique improves the worst-case eye-openings by 38% compared to the baseline design.
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