Off-state Reliability Research Articles

AlGaN/GaN superlattice-based multichannel RF transistors for high linearity and reliability: a simplified simulation approach

Multichannel RF power amplifiers offer high frequency operation, high current and RF power, combined with excellent linearity. 3D and 2D simulation is used to investigate how changes in device architecture impact both the linearity and off-state reliability, allowing an improved linear design which does not compromise reliability. Linearity is assessed by extraction of , and third order intercept (TOI) as a function of gate bias, using a straightforward 2D approximation which is computation time and resource efficient compared to the full 3D simulation normally used for these devices. Off-state reliability is assumed to be linked to dielectric failure, and hence peak electric field as a measure of reliability is evaluated at gate corners and edges using a full 3D simulation. It is found that introducing a channel number-dependent doping in the AlGaN/GaN-based superlattice structure can be used to enable an improved transconductance–linearity. It is also found that there is a strong increase in TOI as gate dielectric thickness or fin width is increased. On the other hand, in order to maintain reliability, increased fin height is found to be essential in order to reduce electric field as dielectric thickness is increased. Finally, a device architecture for improving linearity, power and reduced OFF-state field is suggested.

Investigation of the Off-State Degradation in Advanced FinFET Technology—Part II: Compact Aging Model and Impact on Circuits

Part I of this article revealed that the OFF-state degradation consists of both bias temperature instability (BTI) and hot carrier degradation (HCD) traps in different channel regions. In part II of this article, a compact aging model of OFF-state degradation in advanced FinFETs is developed and validated by silicon data of 7-nm node, including the degradation and recovery phases. The model is capable to cover various types of devices, such as n/p types, core/IO devices, with short/long-channels. Meanwhile, trap contributions over time in different types of FinFETs are discussed based on the model component analysis. The model is implemented into circuit simulators and used to predict circuit aging with OFF-state degradation, for example, a ring oscillator (RO) circuit. The extrapolation result shows that up to 25% degradation is underestimated if the OFF-state reliability is not considered. This work provides a solution for more accurate reliability evaluation of nanoscale circuit design.

Single-Step Electron Beam Evaporation for Schottky/Ohmic Drain in GaN-on-Si HEMTs Fabrication

This letter reports a novel method for fabricating Schottky/ohmic drain for GaN high electron mobility transistors (HEMTs). Without secondary photolithography or secondary metal evaporation, the Schottky/ohmic drain can be obtained by adjusting the direction of the electron beam evaporation. Besides, different metal/semiconductor interfaces can be simultaneously formed at this state, which are beneficial to enhance the shielding effect of the rough ohmic-drain metal morphology and modulate the electric field distribution on the drain side. By using Schottky/ohmic drain technology, the average breakdown voltage calculated from 50 devices each is improved from 895 V (ohmic drain device) to 1205 V for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{L}_{\text {GD}} = 18\,\,\mu \text{m}$ </tex-math></inline-formula> , indicating enhanced off-state reliability characteristics for GaN HEMTs.

Operation and performance of the 4H-SiC junctionless FinFET

This work presents a comprehensive study on the behaviour and operation of a vertical 1.2 kV 4H-SiC junctionless power FinFET. The increased bulk conduction in the channel of this topology may bring reductions in the channel resistance compared to trench MOSFETs, whose performance is limited by the high interface state density. For this purpose, finite element (FE) simulations are used to examine the operation of this device. It is hence demonstrated that the junctionless FinFET can attain a high average channel drift mobility well above 100 cm2/(Vs), leaving the resistance to be determined by the drift and substrate regions. This allows the FinFET to turn on and reach its steady state current using a much (> 3x) smaller gate overdrive than standard designs. On the other hand, however, the overly high field in the gate oxide, the lack of an efficient mechanism for hole extraction, and the low threshold voltage can cause significant reliability issues. Furthermore, it is shown that the high input capacitance of the FinFET can limit its switching speed to slower levels than in standard trench MOSFETs, which raises the need for further development of the original design proposed for vertical GaN devices. In this context, it is demonstrated that the addition of a p-shield below the trenches can alleviate the off-state reliability issues and increase the speed, while still maintaining a competitive R on ∼ 2mΩ cm2 even without the use of n-JFET enhancement doping.

Numerical Simulation of Enhanced-Reliability Filleted-Gate AlGaN/GaN HEMT

Reliability has been one of the major concerns for AlGaN/GaN high-electron-mobility transistors (HEMTs) over the past decades owing to their high-power operation. Although significant progress has been made in recent years, to position AlGaN/GaN HEMT technology as a disruptive technology, better understanding of reliability phenomena and their enhancement is necessary. Greater strength of physical phenomena such as converse piezoelectric strain, electric field, electron temperature, and Joule heating accelerates the degradation and reduces the lifespan of such devices. A detailed numerical study has been carried out to observe the impact of gate filleting on the performance of a AlGaN/GaN HEMT. It is observed that the converse piezoelectric strain in the AlGaN barrier layer, as well as the electron and lattice temperatures are suppressed due to the filleting of the gate geometry. To understand this more deeply, a comparison is drawn between field-plate rectangular-gate HEMTs and filleted-gate HEMTs with and without a field plate. For the filleted-gate HEMTs with and without a field plate, the electric field and converse piezoelectric strain are lower by 38% and 30%, respectively, as compared with the rectangular-gate HEMT with a field plate. As the filleting radius is increased, the gate leakage current and lattice temperature at the gate/AlGaN interface are reduced and the OFF-state reliability is enhanced, together with a reduction in the converse piezoelectric strain and electron temperature. Based on the presented analysis, a filleted-gate HEMT is proposed as a potential candidate to mitigate damage induced by converse piezoelectric strain, electron temperature, and Joule heating in future AlGaN/GaN-based high-power devices.

Metal-to-metal antifuse with low programming voltage and low on-state resistance

This paper describes and analyses the impact of the Ti layer, which is embedded between the insulator and top electrode, on the programming characteristic of the Al—HfO2—Al antifuse. The programming voltage of the antifuse with 120 Å HfO2 is properly reduced from 5.5 to 4.6 V with an embedded Ti layer. Low on-state resistance (~19 Ω) and low programming voltage (4.6 V) is demonstrated in the embedded Ti antifuse with 120 Å HfO2 while keeping sufficient off-state reliability. The antifuse embedded with a Ti layer between the insulator and top electrode has been developed and has potential in field programmable devices.

Study of the leakage current suppression for hybrid-Schottky/ohmic drain AlGaN/GaN HEMT

The leakage current suppression mechanism in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is investigated. It is known that leakage current can cause severe reliability problems for HEMT devices and conventional AlGaN/GaN HEMT devices suffer from detrimental off-state drain leakage current issues, especially under high off-state drain bias. Therefore, a leakage current suppression technique featuring hybrid-Schottky/ohmic-drain contact is discussed. Through the 2-zones leakage current suppression mechanism by the hybrid-Schottky/drain metal including the shielding effect of the rough ohmic-drain metal morphology and the drain side electric field modulation, AlGaN/GaN HEMT featuring this novel technique can significantly enhance the leakage current suppression capability and improve the breakdown voltage. An analytical method using loop-voltage-scanning is proposed to illustrate the optimization procedure of the hybrid-Schottky/ohmic drain metallization on leakage current suppression. Through the comparison of the loop leakage current hysteresis of conventional ohmic drain HEMT and hybrid-Schottky/ohmic drain, the leakage current suppression mechanism is verified through the leakage current considering surface acceptor-like trap charging/discharging model. Device featuring the hybrid-Schottky/ohmic drain technique shows an improvement in breakdown voltage from 450V (with no Schottky drain metal) to 855V with a total drift region length of 9μm, indicating enhanced off-state reliability characteristics for the AlGaN/GaN HEMT devices.

(Invited) Atom Switch Technology for Low-Power Nonvolatile Logic Application

With the increasing functions in digital circuit, flexibility and energy-efficiency play important roles in addressing future mobile/cloud computing systems. Scaling of CMOS devices and interconnects has contributed to high performance and low power operation of ULSI devices. Due to excessive stand-by power accompanying device shrinking, further scaling is experiencing serious roadblocks, and in near future, scaling will face a physical limit of the device dimension. One of the solutions to enhance device performance without scaling is to introduce “More than Moore” devices, which are integrated on CMOS without increasing the chip-size. Especially, resistive switching devices, such as magnetic random-access memory [1], phase-change memory [2], and electrochemical switch [3-5], have attracted much attention because of their potential for use in not only memory but also logic application.Atom switch is an electrochemical resistive-change device categorized in the cation type [4]. The electrochemical phenomenon is nonvolatile and based on electrolysis of the Cu electrode to produce a precipitation of Cu between the electrodes, which realizing a high ON/OFF conductance ratio. Previously, we reported a replacement of the SRAM-based switch with atom switch integrated in Cu-BEOL (Fig.2) [6]. An elimination of the forming process and high ON/OFF-state reliabilities have been realized by introducing a polymer solid-electrolyte (PSE) [7], a complementary atom switch (CAS) [8] and alloy electrodes [9].As compared to a two-terminal device, a three-terminal device is advantageous for the logic application since the separation of the programming line and signal transfer line simplifies circuit design and reduces the layout area. In this paper, a three-terminal resistive-change device featuring the resistive-change junctions coupled with the diode-inserted gate is discussed. References R. Nebashi, et al., “A 90nm 12ns 32Mb 2T1MTJ MRAM”, IEEE Solid-State Circuits Conference - Digest of Technical Papers, 8-12 Feb. 2009 Page(s):462 - 463,463a. D. Ielmini, et al., “Reliability Impact of Chalcogenide-Structure Relaxation in Phase-Change Memory (PCM) Cells—Part I: Experimental Study”,IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1070-1077, 2009.M. N. Kozicki, et al., “Applications of programmable resistance changes in metal-doped chalcogenides”, Pennington NJ USA: Electrochem. Soc. 298–309 (1999).T. Sakamoto, et al., “Nanometer-scale switches using copper sulfide”, Appl. Phys. Lett.82, 3032, (2003).R. Waser and M. Aono, “Nanoionics-based resistive switching memories”, Nature Material, vol.6, pp. 833-839 (2007).M. Tada, et al., “Nonvolatile Crossbar Switch using TiOx/TaSiOy Solid-electrolyte”, IEEE Transactions on Electron Devices, vol. 57, no.8, pp.1987-1995, (2010).M. Tada, et al.,“Polymer Solid-Electrolyte (PSE) Switch Embedded on CMOS for Nonvolatile Crossbar Switch”, IEEE Transactions on Electron Devices, vol. 58, no. 12, pp.4398-4405, (2011).M. Tada, et al.,“Improved Off-state Reliability of Nonvolatile Resistive Switch with Low Programming Voltage”, IEEE Transactions on Electron Devices, vol. 59, no. 9, pp.2357-2362, (2012).M. Tada, et al.,“Improved On-state Reliability of Atom Switch Using Alloy Electrodes”, IEEE Transactions on Electron Devices, vol. 60, no. 10, pp.3534-3540, (2013).

Methodology for predicting off-state reliability in GaN power transistors

Results of a lifetest across temperature and drain voltage on off-state high power GaN FET test structures are presented. The times to failure (tf) are fitted to a combination of the Arrhenius model (ln(tf)∼inverse temperature) and the linear field model (ln(tf)∼drain voltage). The estimated activation energy (Ea) is 2.1eV and the estimated linear field parameter (γ) is 0.03V−1. Reliability parameters estimated from the test structure data are used to predict the FIT rate for a product level FET using linear scaling of the gate width. Further, the effect of a burn-in and a transient voltage under a duty cycle on the FIT rate are modeled. The FIT rate of the product level FET is larger than that of the test structure. The burn-in and transient voltage similarly reduce the reliability. Contour plots are given that allow trade-offs between these factors in order to meet reliability requirements.

Improved Off-State Reliability of Nonvolatile Resistive Switch With Low Programming Voltage

A complementary atom switch (CAS) is proposed to realize low programming voltage and high off-state reliability for crossbar switch application. Two atom switches with bipolar operation are connected in series with opposite direction, in which the two atom switches work as a single element. The two off-state atom switches in the CAS complementarily divide voltage stress, greatly enlarging the off-state lifetime. The CAS is embedded in Cu BEOL on a 65-nm-node CMOS platform without degrading the CMOS and interconnect performances. The CAS using two atom switches is one of the candidates for realizing energy-efficient nonvolatile programmable switches.

Wafer scale and reliability investigation of thin HfO2·AlGaN/GaN MIS-HEMTs

A wafer scale investigation of AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) fabricated with a 4in. Si CMOS compatible technology is presented in this paper. High performance AlGaN/GaN MIS gated HEMT (MIS-HEMT) and passivated HEMT (i-HEMT) were fabricated using thin HfO2 and CVD Si3N4 as the gate and passivation insulator, respectively. Gate and drain leakage currents as well as dynamic I–V trapping were significantly improved with the MIS-HEMT architecture with almost no trade-off to the on-state. Preliminary assessment of the device off-state reliability has been performed at elevated temperatures up to 310°C.

Off-State Degradation of High-Voltage-Tolerant nLDMOS-SCR ESD Devices

The OFF-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an n+ poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both OFF-state and ESD reliability.

Voltage-Splitting Technique for Reliability Evaluation of Off-State Mode of MOSFETs in Ultrathin Gate Oxides

A simple and practical new methodology is proposed for reliability evaluation of off-state mode in ultrathin oxides. By applying a negative voltage on the gate while the drain region is biased at the operating voltage; the so-called voltage-splitting technique (VST), we successfully resolve the difficulty associated with the unrealistic high drain-bias stress otherwise required, which leads to the excessive damage to oxide integrity in the overlap region. In comparison with a high drain-bias stress, the time-dependent dielectric breakdown measurements using VST show the well-behaved breakdown distribution and correlate with the measured device characteristics. In addition, this methodology may provide a possible method to extrapolate stress data to operational voltage for realistic off-state reliability projection.

A novel BaTiO3/SiO2-based voltage-programmable link applicable to on-chip programmable devices

A novel voltage-programmable link (VPL) with Al/BaTiO3/SiO2/TiW silicide/TiW structure has been developed for programmable device application. A programming cell to evaluate programming behaviour consists of an n-MOSFET and a VPL, which are connected in series. The programming process of the VPL was achieved through the switched n-MOSFET. The amorphous BaTiO3 film, prepared by means of an RF sputtering method, determines the program properties of the VPL owing to its lower breakdown field and metallic components. Sufficient low on resistance less than 10 and low programming voltage below 10 V can be realized by using BaTiO3(120 Å)/SiO2(150 Å) films as insulators while keeping sufficient off-state reliability.

Metal-to-metal antifuse with amorphous Ti-rich barium titanate film and silicon oxide film

This paper is focused on the fabrication of reliable novel antifuse, which could operate at low voltage along with the improvement in off and on-state properties. An antifuse composed of Ti-rich barium titanate/silicon oxide sandwiched between Al and TiW–silicide has been developed for high reliable field programmable devices. The breakdown voltage of an antifuse is properly reduced by using amorphous Ti-rich barium titanate film and leakage current is not significantly increased due to the high quality of silicon oxide. Low on-resistance (46 Ω/μm 2) and low programming voltage (9 V) is demonstrated in these antifuses with a 220 Å double insulator layer while keeping sufficient off-state reliability. A significant capacitance reduction at high operating frequencies is also realized.

Extremely Low ON-resistance Metal-to-Metal Antifuses with Al–Cu/10 nm-thick p-SiNx/Al–Cu Structure for Next Generation Very High Speed FPGAs (Field Programmable Gate Arrays)

We present a novel metal-to-metal antifuse structure consisting of a plasma enhanced CVD (chemical vapor deposition) silicon nitride (p-SiNx) dielectric film sandwiched between two aluminum layers. The leakage current in the off-state is markedly reduced by using aluminum film as the upper electrode instead of Ti (titanium) or TiN (titanium nitride) film. A Al–Cu/10 nm-thick p-SiNx/Al–Cu structure antifuse provides sufficient long-term off-state reliability exceeding ten years at 3.6 V while keeping low breakdown voltage (10 V). An extremely low on-resistance of around 3 Ω and a narrow distribution are also realized. A new antifuse structure (Al–Cu/p-SiNx/Al–Cu(100 nm)/Ti/TiN/Al–Cu) highly compatible with the conventional via formation process in double metal interconnect wiring is proposed. This type of antifuse structure is very promising for next-generation very high-speed FPGAs.

High-performance metal/silicide antifuse (for CMOS technology)

A low-programmed-resistance low-thermal-budget, high-performance metal/silicide antifuse is reported. The programmed ON-State resistance of the metal/silicide antifuse is around 60 Omega , which is a factor of 10 less than that of Si-based antifuses (poly/n/sup +/ and poly/poly). Metal/silicide antifuses also eliminate the nonlinear ON-state resistance seen in Si-based antifuses. Programming of the antifuse can be done in 2 ms at 14 V, which is comparable to Si-based antifuses. Both ON- and OFF-state reliability of the metal/silicide antifuse are shown to be satisfactory.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>