Off-state Leakage Current Research Articles

AlGaN/GaN HEMTs With Low Leakage Current and High On/Off Current Ratio

In this letter, we propose using an oxide-filled isolation structure followed by N2/H2 postgate annealing to reduce the leakage current in AlGaN/GaN HEMTs. An off-state drain leakage current that is smaller than 10-9 A/mm (minimum 5.1 × 10-10 A/mm) can be achieved, and a gate leakage current in the range of 7.8 ×10-10 to 9.2 × 10-11A/mm (V GS from -10 to 0 V and V DS = 10 V) is obtained. The substantially reduced leakage current results in an excellent on/off current ratio that is up to 1.5 × 108. An improved flicker noise characteristic is also observed in the oxide-filled devices compared with that in the traditional mesa-isolated GaN HEMTs.

A model for radiation-induced off-state leakage current in N-channel metal-oxide-semiconductor transistors with shallow trench isolation

A radiation-induced leakage current model in deep submicron bulk silicon N-channel metal-oxide-semiconductor field effect transistor (NMOSFET) is proposed in this paper for circuit simulations. The model takes into account the impact of the substrate doping concentration, the angle of shallow trench isolation (STI) region, and the junction depth of source/drain, which can predict the off-state leakage current of the NMOSFET with STI region irradiated at different radiation doses. The model is verified by comparing with the experimental results. The model can be easily implemented into the circuit simulator to evaluate the impact of total ionizing dose effect on the performance of circuit.

Reduction of Off-State Currents in Silicon on Glass Thin Film Transistor by Off-State Bias Stress

We have studied the impact of off-bias stress on the performance of thin film transistors (TFTs) fabricated on single crystalline silicon-on-glass substrates. The p-channel TFT transfer characteristics typically exhibit excellent on-state performance with a field-effect mobility of 203 cm 2 /V s and a subthreshold swing of around 200 mV/dec. However, the off-state drain current has increased with increasing gate voltage. This increasing off-state current phenomenon can be significantly reduced by performing an off-state bias for 10 s. The formation of electron traps in the gate oxide near the drain is the main factor that reduces the off-state leakage current.

High Performance of Ge nMOSFETs Using $\hbox{SiO}_{2}$ Interfacial Layer and TiLaO Gate Dielectric

Using a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfacial layer and a high-¿ gate TiLaO dielectric, the TaN/TiLaO/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /(V · s) at 0.5 MV/cm, and a very low off-state leakage current of 3.5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/¿m. The self-aligned and gate-first metal-gate/high-¿ and Ge nMOSFETs were processed using standard ion implantation and 550°C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.

Low-Standby-Power Bulk MOSFET Design Using High-$k$ Trench Isolation

High-permittivity trench isolation (HTI) is proposed as a means to achieve low off-state leakage current without a high-aspect-ratio or ultrathin body structure. The HTI provides for improved capacitive coupling between the gate and the active region sidewalls, which allows the steep-retrograde body-doping profile to be recessed while suppressing short-channel effects. The result is a lower body-doping concentration at the drain junction, resulting in ~ 10times lower band-to-band tunneling leakage than for a conventional bulk MOSFET design.

Formation of n-channel polycrystalline-Si thin-film transistors by dual source/drain implantation

Formation of n-channel poly-Si TFT devices by the dual source/drain (S/D) implantation scheme has been studied. By the dual-implantation scheme that performs both the high-energy/low-dose large-angle-tilt-implantation and the n +-S/D implantation in the same mask layer, lightly doped n −-region can be effectively formed without needing extra process steps and photo-mask layer in CMOS process integration. As a result, the off-state leakage current of the resultant TFT devices is significantly improved to be about two orders smaller than that for the conventional samples that just receives single n +-S/D implantation, attributable to lower electric field intensity near the drain region. However, by the dual-implantation scheme that employs high-energy/low-dose implantation with no tilt angle, namely as a conventional double-diffused drain scheme, the resultant device characteristics are just comparable to those caused by the conventional scheme.

Improved Poly Gate Engineering for 65 nm Low Power CMOS Technology

A design for the polycrystalline gate is developed for low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The asymmetry characteristics of the device are also improved by the poly deposition. The of the cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well asymmetry.

Simulation of Two-Dimensional 50 nm Vertical Metal Oxide Semiconductor Field-Effect Transistor Incorporating a Dielectric Pocket

A vertical metal oxide semiconductor field-effect transistor (VMOST) incorporating a dielectric pocket (DP) with epitaxial growth has been presented using two-dimensional simulation tools. A comparison between the non-DP VMOST and DP-VMOST was performed. It was shown that DP-VMOST had a better output than non-DP VMOST. The DP-VMOST with a body doping concentration of 2 ×1018 cm-3 and a spacing between the pocket and the gate oxide, WC, of 5 nm resulted in a threshold voltage of 0.35 V, an off-state leakage current of 1.31 ×10-8 A/µm, a subthreshold slope of 76.2 mV, and a drain current of 1069.77 µA/µm. For non-DP VMOST, the results showed a lower threshold voltage and a higher off-state leakage current. The dielectric pocket allowed the suppression of short-channel effects and punchthrough drain to the body. A comparison of the simulation results with experimental results by other researchers has also been performed with ISE simulation software.

Characterization of current injection mechanism in Schottky-barrier metal-oxide-semiconductor field-effect transistors

We discuss the carrier injection mechanism from source/drain to a channel in the on/off-state of Schottky-barrier silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor by developing a refined extraction method for estimation of the Schottky-barrier height. This method is applied to validate the suggested mechanism by utilizing the dummy-gate in an underlap device with a thicker spacer and applying back-gate bias to SOI wafer. The results clearly show that the tunneled carriers from the drain side drive the off-state leakage current. In contrast with the conventional leakage path, the leakage current flows along the interfacial surface of the channel rather than a path underneath the channel.

Anomalous Nickel Silicide Encroachment in n-Channel Metal–Oxide–Semiconductor Field-Effect Transitors on Si(110) Substrates and Its Suppression by Si+ Ion-Implantation Technique

A novel low-leakage-current nickel self-aligned-silicide (SALICIDE) process in n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) on Si(110) substrates is reported. Anomalous nickel silicide encroachment in the <110> direction in nMOSFETs on Si(110) substrates is found for the first time. This encroachment causes anomalous off-state leakage current (Ioff) in nMOSFETs on Si(110) substrates. In particular, in the case of the <110> channel on Si(110) substrates, Ni atoms easily diffuse in the <110> direction, and nickel silicide preferentially grows in the <110> direction. As a result, anomalous leakage current between the drain and the source occurs, and the leakage current seriously degrades transistor performance. In order to overcome these problems, we propose a method of suppressing anomalous Ioff on Si(110) substrates by Si+ ion-implantation technique prior to the nickel SALICIDE process. This method is effective for suppressing the encroachment of nickel silicide and realizing low-leakage complementary metal–oxide–semiconductor (CMOS) devices on Si(110) substrates.

PMOSFET Off-state Leakage and Junction Leakage Current in Ge-based Devices

The impact of the post-implantation Rapid Thermal Anneal (RTA) temperature on the leakage current of p+n junctions fabricated in epitaxial Ge-on-Si substrates is analyzed in terms of the area and the peripheral leakage current component. While the former is not clearly affected, it is shown that the peripheral leakage current density increases in the range 500 to 600oC. A similar trend is found for the off-state leakage current of pMOSFETs made in the same substrates. This is ascribed to a higher activation of the halo implantation, which generates a higher band-to-band tunneling at the interface. It is, finally, shown that replacing the standard BF2 extension implantation by a Ge pre-amorphization followed by a low-energy B implant improves the area leakage current density, most likely because of a lower residual damage.

New Method for Evaluating Electric Field at Junctions of DRAM Cell Transistors by Measuring Junction Leakage Current

A new method for the analysis of dynamic random-access memory (DRAM) data-retention characteristics is developed. We extend a 1-D model of the bias dependence of the electric field in a p-n junction in DRAM to a 2-D model. The validity of the new model is confirmed by simulations and experiments. We then find that the electric-field strength in DRAM can be easily evaluated by measuring the substrate-bias dependence of the off-state leakage current of DRAM by using a test element group. The simulated electric-field strength does not always correspond to actual situations, so our method is very useful to monitor the electric-field strength in an actual device. Furthermore, we experimentally confirm that the electric field in DRAM strongly affects the tail-t ret, which is the worst case of the retention-time distribution. We confirmed that the relationship between the tail- t ret and the electric-field strength in DRAM is constant even if gate length changes. On the other hand, we confirmed that the tail-t ret becomes lower with an increasing number of defects around the p-n junction in DRAM even if the electric-field strength does not change. At the development stage, comparing data of electric-field strength and tail-t ret measured in preproduction samples to those in previous products, we can determine which method is more effective to increase tail- t ret:lowering the electric-field strength or reducing the number of defects in devices. Our method for evaluating an electric field is applicable to all generations of DRAM, so it will be a powerful tool for the design of DRAMs with an adequate retention time.

AlGaN channel HEMTs on AlN buffer layer with sufficiently low off-state drain leakage current

The buffer layer in AlGaN channel HEMTs to suppress the off-state drain leakage current is investigated. By employing an AlN for the buffer layer in Al 0.39 Ga 0.61 N/Al 0.16 Ga 0.84 N HEMTs, the off-state drain leakage current was sufficiently suppressed and the breakdown voltage was enhanced. It was considered that employing the AlN for the buffer layer is important for extracting the superior material properties of the AlGaN in the channel layer.

Degraded off-State Current of Organic Thin-Film Transistor and Annealing Effect

We report a significant increase in the off-state leakage current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) of an organic thin-film transistor with polystyrene (PS) gate dielectric following air exposure. The increased <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> was found to be caused by the degradation of the PS insulation property. The gate leakage current continuously increased, following air exposure for four weeks. Interestingly, the gate leakage current was reduced after the degraded device underwent annealing at 70degC which is lower than the PS glass temperature. The change in the gate leakage is well correlated with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> shift observed in both the air exposure and the following anneal. Based on the observation, we believe that the enhancement of the leakage is likely attributed to the trap generation inside the PS layer.

Gate-Length and Drain-Bias Dependence of Band-to-Band Tunneling-Induced Drain Leakage in Irradiated Fully Depleted SOI Devices

The effects of gate length and drain bias on the off-state drain leakage current of irradiated fully-depleted SOI n-channel MOSFETs are reported. The experimental results are interpreted using a model based on the combined effects of band-to-band tunneling (BBT) and the trapped charge in the buried oxide. For negative gate-source voltages, the drain leakage current increases with the drain voltage because the electric field in the gate-to-drain overlap region is increasing. The off-state current in these devices increases with total ionizing dose due to oxide trapped charge build up in the buried oxide, enhanced by the BBT mechanism. The experimental data show that these effects are more significant for devices with shorter gate-lengths. Simulation results suggest that the BBT-generated holes are more likely to drift all the way from the drain to the source in shorter devices, enhancing the drain leakage current, while they tend to tunnel across the gate oxide in longer devices.

UV Illumination Technique for Leakage Current Reduction in a-Si:H Thin-Film Transistors

The high photoconductivity of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) is responsible for the leakage current under illumination-particularly in projectors and displays with high-intensity backlight illumination. This work investigates a leakage current reduction approach, in which the inverted staggered a-Si:H TFTs are exposed to the ultraviolet (UV) laser. An 85% reduction in the leakage current in a-Si:H TFTs is experimentally observed. The general SPICE model (such as the RPI model) lacks the proper term to capture the photo-induced phenomena; therefore, the physical mechanisms that are associated with the illumination of a-Si:H TFTs under UV, including the energy state and the density of traps, are analyzed using device simulation. The I-V characteristics of the inverted staggered a-Si:H TFTs under different magnitudes of UV exposure are calibrated with experimentally measured data. The preliminary results show the change of trap states in amorphous silicon film and a shift of the Fermi level with UV illumination. UV illumination may induce traps in the active layer of the device and thereby reduce the OFF-state leakage current.

Characteristics and reliability of a polysilicon thin-film transistor with a multi-trenched body

This paper describes a polysilicon thin-film transistor (TFT) with a multi-trenched body that has been fabricated and found to suppress the off-state leakage current without degrading the on-state current or other electric properties. The thin-film structure minimizes carrier scattering through the polysilicon's grain-boundary traps. In addition to this effect, our multi-trenched structure reduces the off-state current by 50% compared to a conventional TFT. The effects of high temperature and dc hot-carrier stress are also measured in comparison to a conventional TFT. At 100 °C, the multi-trenched-body TFT has a higher output saturation current. After 10 000 s of stress testing, the trench-bodied structure continues to outperform the conventional TFT.

Predicting Method of Leakage Current in Multiple-Gate Amorphous Silicon TFTs for Active-Matrix Electrophoretic Displays

The large off-state drain-source leakage current of the thin-film transistor (TFT) in active-matrix electrophoretic display (AMEPD) may cause severe crosstalk and long pixel refresh time. Multiple-gate amorphous silicon TFT (a-Si TFT) is a common use to overcome this issue. In this paper, we show that the leakage current of multiple-gate a-Si TFT can be computed from the - characteristics of a single TFT by an analytical current model. The predicted leakage currents show good agreement with the expected values in SPICE simulation. This model is also applicable for the multiple-gate a-Si TFTs used in other high voltage driven devices.

A High-Performance Polysilicon Thin-Film Transistor Built on a Trenched Body

In this paper, a high-performance polysilicon thin-film transistor (poly-Si TFT) with a trenched body is proposed, fabricated, and studied. This new trenched TFT can be easily produced by filling and etch-back technology without destroying the channel film quality. The addition of the body trench is found to reduce the off-state leakage current by 70% on average, because the trench induces a carrier scattering effect in the poly-Si grain-boundary traps, thereby affecting the leakage path. Although the off-state current is substantially reduced, the on-state current is comparable with that of a conventional TFT. Our multiple-trenched-body TFT is also shown to improve the breakdown voltage by 11%.

The formation of polycrystalline-Si thin-film transistors with a thinned channel layer

Polycrystalline-Si thin-film transistors with a thinned channel layer have been examined. A thinner channel layer may yield a larger on-state current, due to better gate control over the entire channel region. In addition, a thinned channel layer can also reduce the source/drain bulk punch-through and thus the lateral electric field within the channel region. As a result, a 20 nm thick channel layer can significantly suppress the leakage current at relatively large negative gate voltages better than the 100 nm thick channel layer. However, a thinner channel layer would lead to more bending of the energy band at an applied gate voltage, thus enhancing the vertical electric field. Accordingly, when a channel length of 1 µm is examined, the 20 nm thick channel layer would resultantly cause a lowest leakage current (off-state current) value a half-order larger than the 100 nm thick channel layer. Hence, from the device aspect, a properly thinned channel layer, which is of 30 nm thickness here, can be employed to achieve a large on-state current without considerable degradation of the off-state leakage current, while suppressing the leakage current induced at relatively high negative gate voltages.