Off-chip Drivers Research Articles

A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-/spl mu/m DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines, local sense amplifier, and fully shielded data lines without area penalty have provided improved data access time and, thus, high data rate can be achieved. Off-chip driver with calibrated strength and on-die termination are utilized to give sufficient signal integrity for over 533-Mb/s/pin operation.

Clock-deskew buffer using a SAR-controlled delay-locked loop

A successive approximation register-controlled delay-locked loop (SARDLL) has been fabricated in a 0.25-/spl mu/m standard n-well DPTM CMOS process to realize a fast-lock clock-deskew buffer for long distance clock distribution. This DLL adopts a binary search method to shorten lock time while maintaining tight synchronization between input and output clocks. The measured lock time of the proposed SARDLL is within 30 clock cycles at 100-MWz clock input. The power dissipation is 3.3 mW (not including off-chip driver's) at a 1.1-V supply voltage while the measured rms and peak-to-peak jitter are 11.3 ps and 95 /spl mu/s, respectively.

Figures-of-merit for package electrical roadmaps

Transient currents created by on-chip switching in cores and by off-chip drivers cause noise to be generated on package parasitics. Simple mathematical models for the noise are used to derive figures-of-merit for the two cases of on-chip and off-chip switching. SIA Roadmap packaging trends are used with the figures-of-merit to produce package noise trends.

1 Gbit/s CMOS photoreceiver with integrated detector operating at 850 nm

A fully integrated single-beam optical receiver is realised in a production 0.35 /spl mu/m CMOS process, which operates at 850 nm to 1 Gbit/s. The receiver integrates a photodiode, preamplifier, digital logic, and an off-chip driver. Pre-amplifier dissipation is <1.5 mW at 2.3 V, with an average optical power of -6.3 dBm required for 1 Gbit/s operation. Such a compact optical receiver may be of interest for short distance optical interconnects or local area networks.

Low-noise CMOS preamplifier-shaper for silicon drift detectors

We have designed a 16-channel preamplifier-shaper for particle tracking using silicon drift detectors (SDD). The preamplifier, which is optimized for a detector capacitance of 0.2-0.8 pF, uses two new circuit techniques to achieve a low noise (ENC 120 e/sup -/+62 e/sup -//pF), high linearity (<0.5% to 50 fC), and good tolerance to process variations and temperature and power supply fluctuations. The circuit is continuously sensitive, has no digital signals on chip, and requires no external components or critical adjustments. The peaking time of the shaper is 50 nsec and the power dissipation, including an off-chip driver, is 6.5 mW/channel. The circuit is fabricated in 1.2 /spl mu/m CMOS and can accommodate detector leakage currents of up to 1.5 uA. Although the circuit was developed for use with particle tracking detectors, these techniques are also well-suited for the design of lower-noise preamplifiers for high-resolution X-ray spectroscopy systems.

LOW POWER DESIGN OF OFF-CHIP DRIVERS AND TRANSMISSION LINES: A BRANCH AND BOUND APPROACH

As electronic systems grow in functional complexity, hence size, the design is often forced into a multi-chip solution. For such systems, the power dissipation due to the off-chip drivers (OCDs) and the off-chip interconnect capacitance can contribute to a significant portion of the overall system power. Often, however, this excessive power dissipation is unwarranted, since a smaller OCD can be used to drive the transmission line load, hence reducing the net capacitance being switched. The objective of this paper is to enable power dissipation trade-off decisions during the high-level phases of design and to minimize the power dissipation of OCDs and their associated interconnect. First, a termination metric is described that uses width optimization of RLC interconnects. Then, in terms of a proposed linear driver model, the low power design objective is posed as an integer programming problem and a branch and bound enumeration algorithm is presented. The driver and interconnect sizes are determined which will preserve signal quality, dispense with additional termination components, meet delay requirements, and minimize the overall power dissipation.

Design trade-offs for the last stage of an unregulated, long-channel CMOS off-chip driver with simultaneous switching noise and switching time considerations

Design trade-off relations for the last stage of a complementary metal-oxide-semiconductor (CMOS) off-chip driver that meets a prespecified normalized maximum simultaneous switching ground noise and a prespecified normalized time when the switched N-channel metal-oxide-semiconductor transistor (NMOST) leaves the saturation region are provided in this paper. To maintain system performance with control of 90-10% fall time and/or 10-90% rise time, the proposed trade-off relations are then modified numerically for design with prespecified fall/rise time. The proposed trade-offs relate the normalized simultaneous switching noise and the normalized switching time to driver size, load capacitance, ground/power path inductance, number of switching drivers, and input signal rise time. It will be shown that a dimensionless analysis method allows design to be extended to a variety of systems that share the same dimensionless performance. Such a feature will be demonstrated by SPICE simulations of circuits based upon the proposed design relations and MOS1 model, which agrees well with the design goals.

Switching codes for delta-I noise reduction

In this paper, we address the off-chip driver delta-I or switching noise problem. We propose a novel approach based on switching codes to reduce this noise. These codes are designed to lower the number of drivers which switch in any given system cycle. A formal theoretic framework for switching codes is developed which provides an upper bound on the number of switching drivers as a function of bit width of the data bus and number of redundant switch bits. Switching codes with error detecting and error correcting capabilities are also presented. Switching codes also reduce the average switching activity and power consumed by the off-chip drivers.

Modeling, measurement, and simulation of simultaneous switching noise

The computer package designer depends on modeling power supply noises to ensure that system designs will function properly. Power supply noises can have a tremendous effect on system operation and performance. The circuit simulation of a system power distribution is very challenging since it requires accurate models of active devices, passive components, transmission lines, and a very large power distribution network. This paper presents the development of a high-frequency power distribution model for the simulation of simultaneous switching noise of a complementary metal-oxide-semiconductor (CMOS) chip on a multilayered ceramic substrate. Measurements are performed on a CMOS chip with simultaneously switching off-chip drivers (OCD's). The modeling approach is validated by the excellent agreement between the measurement waveforms and simulation results.

Effects and modeling of simultaneous switching noise for BiCMOS off-chip drivers

A model of simultaneous switching noise (SSN) for the conventional BiCMOS driver including the influence of negative feedback is presented. Level 1 SPICE-type MOSFET and Gummel-Poon BJT device models are used for the analysis. The model accounts for a reduction in forward current gain, /spl beta//sub F/, that is attributed to high-level injection effects. Closed-form expressions are presented that predict the maximum SSN encountered in low-level and high-level injection. Solutions of the first equation are combined with the second in order to model the complete SSN transient. Model predictions are compared to SPICE simulation results for 5 V, 1 /spl mu/m drivers and 3.5 V, 0.5 /spl mu/m drivers with close agreement. The effects of BJT parasitic resistance, junction capacitance, and forward transit time on reducing induced ground noise are also explored. With the introduction of these parasitics, SPICE predictions of the maximum SSN are approximately 20% lower than closed-form model results. Immunity of the quiet BiCMOS driver to noise present at the ground and power connections is also investigated. It is found that the quiet driver is highly immune to adverse effects caused by SSN at the power connection and partially immune to SSN present at the ground. Coupling between ground noise and the output occurs when the ground noise is greater than two forward diode drops above ground, in which case the output tracks the ground noise with a negative offset of one diode drop.

A low-noise TTL-compatible CMOS off-chip driver circuit

Low-noise TTL-compatible off-chip driver (OCD) circuits are very important, especially for low-power electronics, but scaled-down CMOS technology requires a lower operating voltage of 3.3 V, while most applications require 5 V. The dual power-supply requirement makes the design of OCD challenging, first because pull-up devices, especially p-MOS devices, must be able to handle an off-chip voltage of 5.6 V, which is higher than an on-chip VDD of 2.8 V, and second because pull-down devices should be able to discharge a capacitive load of 5.6 V while operating at a minimum on-chip VDD of 2.8 V. This extreme difference in operating voltage makes the circuits susceptible to ringing and performance degradation due to hot-electron effects. In this paper, we describe a low-noise OCD which has been successfully used in IBM second-generation 4Mb low-power DRAM (LPDRAM) and in other products. For pull-ups, two stacked p-MOS devices with floating n-wells are used, but they are operated in different modes dependi ng on the supply voltage. The pull-down devices are basically composed of two stages, one of which is in the diode configuration with its gate and drain shorted together during the pull-down. Detailed circuit designs to achieve low noise while meeting the performance requirements are described.

Relative figures of merit for chip-to-MCM substrate interconnection methods

Functional performance of an electronic system is proportional to the functional throughput rate, which is defined as the product of the function density (gates/cm/sup 2/) and the clock rate. Various chip-to-module assembly methods for high-density substrates can provide a functional throughput rate approaching that of the integrated circuit (IC). Results of a comparative study for the performance of simultaneously switching off-chip drivers in various multichip module (MCM) scenarios are reported for CMOS and emitter-coupled-logic (ECL) technologies. Flip-chip technology can provide up to twelvefold improvement in performance over tab automated bonding (TAB) for a CMOS system, and about sevenfold improvement for an ECL system. However, when the delay in the critical path is dominated by on-chip circuits, speed improvement by MCM becomes negligible. Electrical parasitics of the chip-to-substrate interconnections also create undershoot in the switching signal, which reduces the noise margin. It is concluded that the advantages of high-density multichip packaging, in decreasing order of importance, are density of integration, reduction in the switching noise, shorter off-chip delays, and reduction in power dissipation. >

Partitioning and floor-planning for data-path chip (microprocessor) layout

Data-path chips are typically made up different types of objects such as data-path macros, control logic cells (e.g. standard-cell), memory arrays, and off-chip drivers. Each type of object is quit...

A high-speed dynamic domino circuit implemented with GaAs MESFETs

The dynamic domino and gates composed of GaAs depletion-mode (D-mode) MESFETs are described in this work. This circuit allows very complex input combinational functions which can provide very high gate equivalences. Test circuits were designed which consisted of chains of 15 dynamic AND gates with static off-chip drivers. The circuits were fabricated by a foundry and tested at the wafer level. The measured propagation delay per gate is 180 ps for a two-input AND gate and 220 ps for a four-input AND gate, with a power consumption of 0.55 mW/gate. The minimum frequency of operation is found to be as low as 100 kHz. A 4-b carry generator was designed and simulated. A delay of 400 ps was predicted for this circuit.

Open-loop gain limitations for push-pull off-chip drivers

Open-loop gain limitations are described for a novel type of off-chip driver (OCD). This OCD uses feedback to make the output signal track an internal ramp. By gain adjustment, the driver impedance is matched to the output transmission line.

Optimal choice of intermediate latching to maximize throughput in VLSI circuits

In many computational tasks, especially in signal processing, it is the throughput that is important, rather than the latency, or delay. If a special-purpose VLSI chip is designed for a particular signal processing task, such as FIR filtering, for example, the maximum clock rate, and hence throughput, is determined by the depth of the combinational logic between registers and the time required for the distribution and operation of the clock. If the combinational logic is sufficiently deep (in bit-parallel circuits, for example), the throughput can be increased by inserting intermediate stages of clocked latches. This is at the expense of increased area and delay to operate and clock the intermediate registers. Roughly speaking, the strategy amounts to using more of the chip area to store information useful for pipelining. This paper investigates the optimal tradeoff between the degree of intermediate latching and cost, using the measure AP, where A is the chip area and P is the period (the reciprocal of throughput). We derive expressions for the time and area before and after intermediate latching, using the Mead-Conway model, both for the cases of on-chip and off-chip clock drivers. The results show that significant reductions in AP product (reciprocal of throughput per unit area) can be achieved by intermediate latching in many typical signal processing applications, for a wide range of circuit parameters. The array multiplier is used as an example.

The Thin-Film Module as a High-Performance Semiconductor Package

This paper discusses a multichip module for future VLSI computer packages on which an array of silicon chips is directly attached and interconnected by high-density thin-film lossy transmission lines. Since the high-performance VLSI chips contain a large number of off-chip driver circuits which are allowed to switch simultaneously in operation, low-inductance on-module capacitors are found to be essential for stabilizing the on-module power supply. Novel on-module capacitor structures are therefore proposed, discussed, and evaluated. Material systems and processing techniques for both the thin-film interconnection lines and the capacitor structures are also briefly discussed in the paper. Development of novel defect detection and repair techniques has been identified as essential for fabricating the Thin-Film Module with practical yields.

A 16-kbit Block Addressed Charge-Coupled Memory Device

This paper describes the design and performance of a 16-kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 /spl mu/W/bit with another 0.5 /spl mu/W/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.

A 16-kbit block addressed charge-coupled memory device

This paper describes the design and performance of a 16- kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 µW/bit with another 0.5 µW/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.

Comments on "An optimized output stage for MOS integrated circuits" [with reply

An interesting approach to improving the performance of MOS off-chip drivers has previously been described (see ibid., vol.10, no.2, p.106 (Apr. 1975)). The selection of the optimization criterion is discussed.