Off-axis Substrates Research Articles

(Invited) High Quality 3C-SiC for MOS Applications

In this work, the growth of high quality 3C-SiC films on Si substrates grown by a hot-wall chemical vapor deposition (CVD) reactor is presented. An increased crystal quality means a reduced crystallographic defect density affecting 3C-SiC films which can be achieved by reducing the growth rate during 3C-SiC heteroepitaxy. In particular, the micro-twin density was observed to decrease with decreasing growth rate allowing for the reduction of theboth the rocking curve and transverse optical Raman mode peak width. Si substrates, both of on- and off-axis orientation, are considered with improvement in crystal quality observed when off-axis substrates are used. Finally, stacking faults and microtwins at the SiC/SiO2 interface are seen to cause non-uniformity in the oxide layer due to the different oxidation rate observed.

(Invited) Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

Epitaxial Growth of 4H-SiC on 4° Off-Axis Substrate for Power Devices

Homo-epitaxial layers are successfully grown on Si-face 4° off-axis 4H-SiC substrates using the horizontal hot-wall chemical vapor deposition system. The smooth surface without morphological defects is obtained by the optimized in situ etching process and growth temperature. Schottky diodes fabricated on the epilayer present a typical I—V characteristic. This is the first report of Schottky diodes fabricated on 4° off-axis 4H-SiC substrates made in China.

Comparative micro-photoluminescence investigation of ZnO hexagonal nanopillars and the seeding layer grown on 4H-SiC

We report on a comparative micro-photoluminescence investigation of ZnO hexagonal nanopillars (HNPs) and the seeding layer grown on the off-axis 4H-SiC substrate. Transmission electron microscope (TEM) results establish that a thin seeding layer continuously covers the terraces of 4H-SiC prior to the growth of ZnO HNPs. Low temperature photoluminescence (LTPL) shows that ZnO HNPs are only dominated by strong donor bound exciton emissions without any deep level emissions. Micro-LTPL mapping demonstrates that this is specific also for the seeding layer. To further understand the recombination mechanisms, time-resolved micro-PL spectra (micro-TRPL) have been collected at 5 K and identical bi-exponential decays have been found on both the HNPs and seeding layer. Temperature-dependent TRPL indicates that the decay time of donor bound exciton is mainly determined by the contributions of non-radiative recombinations. This could be explained by the TEM observation of the non-radiative defects in both the seeding layer and HNPs, like domain boundaries and dislocations, generated at the ZnO/SiC interface due to biaxial strain.

Weak Localization and Universal Conductance Fluctuations on Epitaxial Graphene Grown on the C-Face of 8°off-Axis 4H-SiC Substrates

We report magnetotransport measurements in single epitaxial graphene layers grown on the C-face of an 8° off-axis 4H-SiC substrate using high temperature annealing conditions with a graphite cap covering the sample. The graphene sheets were found p-type doped, with mobilities varying between 1000 and 11000 cm²/V.s from device to device at 1.6 K. We examine the signature of weak localization and universal conductance fluctuations at weak magnetic field and we show that the phase coherence lengths extracted from the two phenomena are in satisfactory agreement.

Growth of smooth 4H-SiC epilayers on 4° off-axis substrates with chloride-based CVD at very high growth rate

4H-SiC epilayers grown on 4° off-axis substrates at high rates usually suffer from step-bunching (very high surface roughness) or of extended triangular defects, both detrimental for device performance. In this study we developed a novel in situ pre-growth surface preparation based on hydrogen chloride (HCl) addition at a temperature higher than that used for the growth. This pre-growth etching procedure minimizes the density of triangular defects which usually occur at low temperatures and simultaneously enables growth at a temperature low enough to reduce step-bunching. Thanks to this surface preparation step, chloride-based chemical vapour deposition (CVD) could be used for rapid epitaxial growth of high quality layers. In this study, layers were grown at rates of 100 μm/h yielding defect free epitaxial layers with very smooth surface (rms value of 8.9 Å on 100 μm × 100 μm area).

Impact of structural defects upon electron mobility in InSb quantum wells

The detrimental effects of structural defects, micro-twins (MTs) and threading dislocations (TDs), on electron mobility have been investigated for InSb quantum wells (QWs) at room temperature (RT). The constants that are necessary to calculate the electron-mobility limits of these defects were determined by a least-squares-based method that has an advantage of clear representation of the analytical results in a two-dimensional space. Based on a mathematical consideration, a general method of converting electron-mobility limits into percentage impacts upon the total electron mobility was developed. Percentage-mobility-impact analyses showed that, when InSb QWs grown on on-axis (001) GaAs substrates have a TD density of 8.7 × 108 – 3.2 × 109/cm2, 21–14 and 18–45% of electron-mobility degradation are attributed to MTs and TDs, respectively, at RT. The use of 2° off-axis (001) GaAs substrates reduces MT densities in InSb QWs, resulting in a suppression of the MT mobility impact to 3–2% and a complementary slight increase of the TD mobility impact to 22–51% in the same TD density range. This considerable TD mobility limit indicates that it should be possible to improve RT electron mobility in InSb QWs grown on 2° off-axis (001) GaAs substrates, by means of reducing TD density further (< 8.7 × 108/cm2). Although the mobility impacts due to phonons in InSb QW grown on-axis and 2° off-axis (001) GaAs substrates are 54–36 and 67–42%, respectively, phonon scattering is not a single dominant scattering factor: MTs and TDs have also substantial negative impacts upon RT electron mobilities in InSb QWs.

Dependence of Process Characteristics on Atomic-Step Density in Catalyst-Referred Etching of 4H–SiC(0001) Surface

Catalyst-referred etching (CARE) is a novel abrasive-free planarization method. CARE-processed 4H-SiC(0001) surfaces are extremely flat and undamaged over the whole wafer. They consist of single-bilayer-height atomic steps and atomically flat terraces. This suggests that the etching properties depend principally on the atomic-step density of the substrate surface. We used on-axis and 8 degrees off-axis substrates to investigate the processing characteristics that affect the atomic-step density of these substrates. We found a strong correlation between the removal rate and the atomic-step density of the two substrates. For the on-axis substrate, the removal rate increased with increasing surface roughness, which increases with an increasing atomic-step density. The removal rate ratio is approximately the same as the atomic-step density ratio of the two substrates.

Influence of Post-Growth Annealing on the Defects Nature and Distribution in VLS Grown (111) 3C-SiC Layers

The current communication focuses on the influence of a post-growth annealing on the evolution of defects inside (111) 3C-SiC layers grown by the Vapour Liquid Solid (VLS) mechanism in SiGe melts on Si-face on- and off axis 6H-SiC substrates. The layers are studied by Transmission Electron Microscopy (TEM) and Low Temperature Photoluminescence (LTPL). It was found that the growth on off-axis substrates results in a 3C-SiC layer containing mainly stacking faults (SFs) and microtwins (MT). The density of MT lamellae and SFs reduces in the layers grown on the on-axis substrate compared to off-axis substrate. In the layers grown on off-axis substrates the annealing strongly reduces the density of SFs inclined to the 3C/6H-SiC interface. Additionally, 3C to 6H polytypic transformation appears only at the interface, most probably starting from substrate step edges. This was only seen on off-axis seed since the step edges are more.

4H-SiC Homoepitaxial Growth on Substrates with Different Off-Cut Directions

Homoepitaxial growth on 4° off-axis substrates with different off-cut directions, i.e. [11-20] and [1-100], was investigated using a commercial CVD reactor. The characteristics of the growth process on substrates with different off-cut directions were determined with respect to applicable C/Si ratio, growth rate and n- and p-type doping range. Stable step flow growth was achieved over a broad range of C/Si ratio at growth rates ~ 15 µm/h in both cases. The n-type doping level of epilayers can be controlled at least in the range from 5  1014 cm-3 to 3  1017 cm-3 on both types of substrates. Highly p-type epilayers with p = 2  1019 cm-3 can also be grown on [1-100] off-cut substrates. Hence, the growth process for standard substrates was successfully transferred to [1-100] off-cut substrates resulting in epilayers with similar doping levels. The dislocation content of the grown epilayers was investigated by means of defect selective etching (DSE) in molten KOH. For both off-cut directions of the substrates, similar densities of threading edge dislocations (TED), threading screw dislocations (TSD) and basal plane dislocations (BPD) were found in the epilayers. Epilayers with very low BPD density can be grown on both kinds of substrates. The remaining BPDs in epilayers are inclined along the off-cut direction of the substrate. The surface morphology and roughness was investigated by atomic force microscopy (AFM). The epilayers grown on [1-100] off-cut substrates are smoother than those on standard substrates.

Geometrical Control of 3C and 6H-SiC Nucleation on Low Off-Axis Substrates

Growth of 3C or 6H-SiC epilayers on low off-axis 6H-SiC substrates can be mastered by changing the size of the on axis plane formed by long terraces in the epilayer using geometrical control. The desired polytype can be selected in thick (~200 µm) layers of both 6H-SiC and 3C-SiC polytypes on substrates with off-orientation as low as 1.4 and 2 degrees. The resultant crystal quality of the 3C and the 6H-SiC epilayers, grown under the same process parameters, deteriorates when lowering the off-orientation of the substrate.

Extraordinary Characteristics of 4H-SiC Trench MOSFETs on Large Off-Axis Substrates

We investigated electrical properties of 4H-SiC trench metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated on (000_,1) C-face substrates with various off-axis angles. Off-axis angles and directions are 4o, 8o, and 15o towards [__,1120] and 8o towards [1_,100] directions. Most trench MOSFETs showed good on-state performance. Peculiar characteristics that field-effect mobility was 103 cm2/Vs in spite of a relatively high acceptor concentration of 1 × 1017 cm−3 in the channel region were observed for trench MOSFET on 15o-off substrates. From crystallographic analysis, this face is (11_,20) with 15o off towards [000_,1] direction. We can expect that this face has quite good MOS interface properties.

Abrasive-Free Planarization of 3-Inch 4H-SiC Substrate Using Catalyst-Referred Etching

Catalyst-referred etching (CARE) is an abrasive-free planarization method. We used 3-inch and 2-inch 4H-SiC (0001) 4° off-axis substrates to investigate the processing characteristics that are affected by the substrate diameter. The surface roughness of the 3-inch substrate was extremely smooth over the whole substrate. The surface roughness and removal rate of the 3-inch substrate were approximately the same as those of the 2-inch substrate.

4H-SiC Epitaxy with Very Smooth Surface and Low Basal Plane Dislocation on 4 Degree Off-Axis Wafer

Improvements in the quality and consistency of 4H-SiC epitaxy wafers are now starting to enable growth of commercial SiC power device applications in areas such as inverters for photo-voltaic systems and power supplies. Recent work has achieved very low epitaxy surface roughness and very low BPD (Basal plane dislocation) in the on 4 degree off-axis substrates. In this paper, we report characterization of the very low BPD epitaxy wafers and a newly observed triangular defect.

High growth rate 4H-SiC epitaxial growth using dichlorosilane in a hot-wall CVD reactor

Thick, high quality 4H-SiC epilayers have been grown in a vertical hot-wall chemical vapor deposition system at a high growth rate on (0 0 0 1) 8° off-axis substrates. We discuss the use of dichlorosilane as the Si-precursor for 4H-SiC epitaxial growth as it provides the most direct decomposition route into SiCl 2, which is the predominant growth species in chlorinated chemistries. A specular surface morphology was attained by limiting the hydrogen etch rate until the system was equilibrated at the desired growth temperature. The RMS roughness of the grown films ranged from 0.5–2.0 nm with very few morphological defects (carrots, triangular defects, etc.) being introduced, while enabling growth rates of 30–100 μm/h, 5–15 times higher than most conventional growths. Site-competition epitaxy was observed over a wide range of C/Si ratios, with doping concentrations <1×10 14 cm −3 being recorded. X-ray rocking curves indicated that the epilayers were of high crystallinity, with linewidths as narrow as 7.8 arcsec being observed, while microwave photoconductive decay (μPCD) measurements indicated that these films had high injection (ambipolar) carrier lifetimes in the range of 2 μs.

Hydride vapor phase epitaxy of high structural perfection thick AlN layers on off-axis 6H-SiC

The employment of more than 10 μm thick AlN epilayers on SiC substrates for AlGaN/GaN high-electron-mobility transistors (HEMTs) substantially raises their performance in high-power energy-efficient amplifiers for 4G wireless mobile stations. In this paper, structural properties and surface morphology of thick AlN epilayers deposited by hydride vapor phase epitaxy (HVPE) on off-axis conductive 6H-SiC substrates are reported. The epilayers were examined in detail by high-resolution X-ray diffraction (XRD), atomic force microscopy (AFM), Nomarski differential interference contrast (DIC), scanning electron microscopy (SEM), and selective wet chemical etching. At optimal substrate preparation and growth conditions, a full width at half-maximum (FWHM) of the XRD rocking curve (RC) for the symmetric (00.2) reflex was very close to that of the substrate (less than 40 arcsec) suggesting low screw dislocation density in the epilayer (∼10 6 cm −2) and small in-plane tilt misorientation. Reciprocal space mapping around asymmetric reflexes and measured lattice parameters indicated a fully relaxed state of the epilayers. The unit-cell-high stepped areas of the epilayers with 0.5 nm root mean square (RMS) roughness over 1×1 μm 2 scan were alternated with step-bunching instabilities up to 350 nm in height. Low warp of the substrates makes them suitable for precise epitaxy of HEMT structures.

Investigation of deep levels in nitrogen doped 4H–SiC epitaxial layers grown on 4° and 8° off-axis substrates

Intentionally doped n-type 4H–SiC films were grown on 4° and 8° off-axis substrates to investigate the influence of electron concentration on the incorporation of electron traps Z1/2 and EH6/7. No discernible change was seen in the Z1/2 and EH6/7 trap concentrations for films grown on both orientations with electron concentrations in the range of 1×1014 to 1×1016 cm−3, suggesting that the Z1/2 and EH6/7 traps are not associated with isolated carbon vacancies. The defect concentrations did not correlate with the measured carrier lifetimes, which is consistent with a carrier lifetime controlled by other recombination centers. Observed decreases in lifetime were related to increases in doping levels, with similar trends seen for both orientations. Carrier lifetimes in 8° material were slightly longer than in 4° films for similar doping concentrations, most likely being associated with surface recombination and/or extended defects.

Properties of lithium phosphorus oxynitride (Lipon) for 3D solid-state lithium batteries

The thin film electrolyte known as Lipon (lithium phosphorous oxynitride) has proven successful for planar thin film battery applications. Here, the sputter deposition of the amorphous LiPON electrolyte onto more complex 3D structures is examined. The 3D structures include off-axis alignment of planar substrates and also 10–100 μm arrays of pores, columns, and grooves. For magnetron sputtering in N2gas at 2.6 Pa, the Lipon film deposition is not restricted to be line-of-sight to the target, but forms conformal and dense films over the 3D and off-axis substrates. The deposition rate decreases for areas and grooves that are less accessible by the sputtered flux. The composition varies, but remains within the range that gives sufficient Li+ionic conductivity, 2 ± 1 μS/cm.

Growth of GaN films on PLD-deposited TaC substrates

GaN films were grown by metal organic chemical vapor deposition on TaC substrates that were created by pulsed laser deposition of TaC onto (0 0 0 1) SiC substrates at ∼1000 °C. This was done to determine if good quality TaC films could be grown, and if good quality GaN films could be grown on this closely lattice matched to GaN, conductive material. This was done by depositing the TaC on on-axis and 3° or 8° off-axis (0 0 0 1) SiC at temperatures ranging from 950 to 1200 °C, and examining them using X-ray diffraction, scanning electron microscopy, atomic force microscopy, and transmission electron microscopy. The GaN films were grown on as-deposited TaC films, and films annealed at 1200, 1400, or 1600 °C, and examined using the same techniques. The TaC films were polycrystalline with a slight (1 1 1) texture, and the grains were ∼200 nm in diameter. Films grown on-axis were found to be of higher quality than those grown on off-axis substrates, but the latter could be improved to a comparable quality by annealing them at 1200–1600 °C for 30 min. TaC films deposited at temperatures above 1000 °C were found to react with the SiC. GaN films could be deposited onto the TaC when the surface was nitrided with NH 3 for 3 min at 1100 °C and the low temperature buffer layer was AlN. However, the GaN did not nucleate easily on the TaC film, and the crystallites did not have the desired (0 0 0 1) preferred orientation. They were ∼10 times larger than those typically seen in films grown on SiC or sapphire. Also the etch pit concentration in the GaN films grown on the TaC was more than 2 orders of magnitude less than it was for growth on the SiC.

Improvement of Surface Roughness for 4H-SiC Epilayers Grown on 4° Off-Axis Substrates

The epitaxial growth process was optimized in order to obtain good surface morphology for epilayers grown on 4˚ off-axis substrates. The optimization was carried out from growth temperatures and gas chemistry including C/Si ratio. Step-bunching was significantly suppressed by the optimized process and a surface roughness Ra of 0.2 nm was achieved. Etch pit density evaluation by KOH etching indicated that the basal plane dislocations were reduced to less than 50 cm-2 by the use of 4˚ off-axis substrates. Photoluminescence evaluation showed that the epilayer grown by the optimized process had a better crystalline quality than that grown by a standard process. Schottky diodes fabricated on the epilayer by the optimized process represented the ideality factor n of 1.01 and the barrier height of 1.67eV. These results demonstrate that high quality epilayers with smooth surfaces comparable to those on 8˚off-axis substrates were obtained on 4˚off-axis substrates.