Off-axis 4H-SiC Research Articles

Buffer Layer Dependence of Defectivity in 200mm 4H-SiC Homoepitaxy

The effect of increasing Buffer Layer (BL) thickness on crystal defectivity has been investigated in 4° off-axis 4H-SiC homoepitaxy on 200mm substrates coming from different suppliers. The results, based on optical microscopy and scatter light methods, show a slight increase in morphological defects in the case of a thicker BL with respect to the standard thickness for both suppliers.

Distribution of basal plane dislocations in 4-degree off-axis 4H-SiC single crystals

The basal plane slip model in 4H-SiC was developed to investigate the effects of off-axis angles on total resolved shear stress. The results showed that the TRSS changed from 6-fold to 4-fold symmetry with the increasing off-axis angles.

Investigating the Distribution Pattern of Threading Edge Dislocation Low Angle Grain Boundaries in 4H-SiC Wafers Using Synchrotron X-Ray Topography

Silicon carbide (SiC) has emerged as a significant wide bandgap semiconducting material, playing a pivotal role in the fabrication of high-frequency, high-power electronic devices in modern times. Its exceptional properties, such as high thermal conductivity, high saturation velocity, and high breakdown field, have positioned it as a valuable constituent in various application fields, including transportation, communication, and bioelectronics. However, the efficacy and long-term reliability of SiC-based devices are critically dependent on the quality of both the SiC substrate and epitaxial material employed. The presence of deleterious defects within these materials can induce device degradation and failure, posing a significant challenge in realizing the full potential of the device. Therefore, it is imperative to address the quality while maintaining the availability of large-scale single crystals of SiC to further expand the development of SiC-based device technology. Among various kinds of crystallographic defects in bulk crystal, low angle grain boundary (LAGB) is a commonly observed planar defect that prevents the implementation of large size (≥ 1 cm2) SiC devices [1]. In both 6H and 4H-SiC, LAGBs have been observed to replicate during the epitaxial growth [2], which can lead to profound impact on the physical and electronic properties of the crystal that subsequently triggers device degradation. Literature reveals that the presence of LAGBs in commercial wafers can lead to increased leakage currents during reverse-bias operation of devices [3]. Besides, the existence of prismatic tilt boundaries is usually accompanied with aggregation of edge type basal plane dislocations (BPDs) [4], which cause severe degradation in SiC bipolar devices [5] as BPD segments can dissociate into partials and form stacking faults in between [6].This study investigated a unique distribution pattern of LAGBs observed on physical vapor transport (PVT) grown off-axis 4H-SiC wafers. Synchrotron X-ray topographs in both transmission and grazing geometry reveal that three sets of LAGBs are presented on one side of the wafer, away from the facet position, each set contains numerous LAGB arrays. Figure 1 (a) shows a schematic diagram where each oval outlines the approximate location of each LAGB set. As the grazing-incidence topographs shown in Figure 1 (b), the LAGB sets distributed at the upper and lower region of the wafer consist of white contrast threading edge dislocations (TEDs) extending from the inner area towards the edge approximately along 60º and 120º direction, respectively. The LAGB set positioned at the middle region of the wafer consists of dark contrast TEDs extending from the inner area towards the edge approximately along 90º direction. All individual TED arrays in each LAGB set extends along the <1-100> directions, with identical Burgers vectors perpendicular to the array direction. The white and dark contrast of TEDs corresponds to tilt in opposite directions. White contrast TEDs are with Burgers vectors of 1/3[2-1-10] and 1/3[1-210], dark contrast TEDs are with Burgers vectors of 1/3[-2110] and 1/3[-12-10]. Such TED LAGBs are identified as pure tilt boundaries that accommodate the rotational misorientation between two adjacent regions. Therefore, a flat wafer is expected to exhibit zero net misorientation due to these TED arrays. However, any non-zero net misorientation resulting from these arrays is likely to promote instability, ultimately leading to the curvature of the plane. A systematic analysis is being carried out across several wafers and this relationship between the distribution of TED arrays and lattice curvature will be discussed.Reference:[1] N. Ohtani et al. Journal of Crystal Growth 237–239, 1180–1186, (2002).[2] C. Hallin et al, J. Cryst. Growth 181, 241 (1997).[3] R. Singh and M. Pecht, IEEE Industrial Electronics Magazine, 2, 19-31, (2008).[4] Y Chen et al, Materials Science Forum 556, 231-234 (2007).[5] T. Kimoto, et al., Proc. IEEE Int. Rel. Phys. Symp., 2A-1.1–2A-1.7, (2017).[6] M. Dudley, et al, Materials Science Forum, 600-603, 261-266 (2008). Figure 1

Synchrotron X-Ray Topography Studies for Defect Formation at the Early Stage of PVT-Grown 4H-SiC Crystals

Silicon Carbide (SiC), typically 4H-SiC, is replacing conventional silicon materials for high power and high frequency applications due to its excellent electrical and thermal properties [1]. However, high quality SiC wafers with low defect density are still in urgent need for automotive and energy saving applications. SiC wafers are obtained from bulk growth by physical vapor transport (PVT) method and considerable efforts have been expended to optimize growth process to lower defect densities. One major approach is the study of initial stages of crystal growth as most defects are nucleated at this stage and propagate into the boule. Ailihumaer et al [2] demonstrated the behaviors of threading edge dislocations (TEDs), threading screw dislocations (TSDs)/threading mixed dislocations (TMDs), and basal plane dislocations (BPDs) across the seed/newly grown layer interface in PVT-grown 4H-SiC. Sanchez et al [3] revealed the nucleation of TEDs and TSDs at the initial growth stage in PVT-grown SiC.However, more detailed investigations are still in demand for PVT grown 4H-SiC crystals during initial stage of growth. This study investigates 4° off-axis 4H-SiC wafers with several hundred microns of initial-stage growth PVT method. Synchrotron X-ray topography (SXRT) technique is employed and shows dramatically modified defect distribution across the seed/newly grown layer interface (Figure 1). The formation of Shockley stacking fault starting at initial stage of crystal growth is suggested as partial dislocations running along <11-20> directions on basal plane are observed to form rhombus shapes (Figure 2). Prismatic slip is observed to take place near the wafer edges and prismatic dislocations undergo cross slip to form unique dislocation configurations. A statistical analysis on defect changes across the seed/newly grown layer is being carried out and the results will be reported. These results will be complemented by observations from Nomarski optical microscopy (NOM) and Raman Spectroscopy studies to propose the formation mechanism of defects across the seed/newly grown layers.

Investigation of defect formation at the early stage of PVT-grown 4H-SiC crystals

Several 4° off-axis 4H-SiC wafers with several hundred microns of initial-stage growth by PVT method are investigated by Synchrotron Monochromatic Beam X-ray Topography (SMBXT). Defect behavior across the seed/newly grown layer interface are demonstrated. Comparison of early stage grown layers to seed sample indicates generation of threading edge dislocation (TED) and threading screw dislocation (TSD)/ threading mixed dislocation (TMD) pairs at the interface while most basal plane dislocations (BPDs) are deflected into TEDs. The (0001) facet of the crystal is already formed at early stage growth at the edge of the wafer and high nitrogen incorporation in facet leads to conditions favorable for nucleation and glide of Shockley/double Shockley faults with layers of 3C-SiC deposited on facet acting as nuclei. Unique-shaped dislocations are observed at early stage growth, which are caused by deflection of TSDs/TMDs and TEDs by macrosteps near the periphery of the sample and the subsequent glide of the a components. The effect of the quality of the seed surface before growth is manifested as randomly oriented arrays of pairs of TEDs and TSDs/TMDs on the as grown surface resulting from residual surface damage from scratches.

Chemical vapor deposition growth of [formula omitted] on Si- and C- face off-axis 4H–SiC at high temperature

Realization of β‐Ga2O3 on a high-thermal-conductivity substrate is crucial to overcome the poor thermal conductivity of β‐Ga2O3 which is one of the major roadblocks against its era in power electronics. We investigated low-pressure chemical vapor deposition (LPCVD) growth on both Si and C- face (0001) 4H–SiC at a high growth temperature of 925 °C using Ga metal and O2 gas source. Growths on C-face 4H–SiC resulted polycrystalline β‐Ga2O3 for the entire O2-flow range, whereas under optimized O2-flow conditions, step flow growth of (−201) β‐Ga2O3 was achieved on Si-face 4H–SiC with 3.7 nm rms surface roughness and rocking curve FWHM of 0.54° at a growth rate reaching 2.48 μm/h 4° off-axis nature of the substrate promoted the growth of some of the in-plane rotational domains while suppressing others. Raman measurements further verified the pure β‐Ga2O3 nature of the grown films. Using a customized LPCVD with solid source Ga, a cost-effective, safe and industrially scalable method was shown to pave the way to enable β‐Ga2O3 heteroepitaxy on 4H–SiC for high-power electronics.

Layered Epitaxial Growth of 3C/4H Silicon Carbide Confined by Surface Micro-Nano Steps

In this study, we used a horizontal hot-wall CVD epitaxy apparatus to grow epitaxial layers on 4° off-axis 4H-SiC substrates. Epitaxial films were grown by adjusting the flow rate of the source gas at different levels. With an increase in the source gas flow rate, a notable transition in the crystalline structure of the epitaxial layer was observed, gradually shifting from 4H-SiC to 3C-SiC. Furthermore, the quality of the epitaxial layer correspondingly exhibited degradation. Specifically, for epitaxial films grown under moderate gas flow rates, the central region demonstrated a crystalline structure of 4H-SiC, while the outer ring region exhibited a crystalline structure of 3C-SiC. Using a scanning electron microscope (SEM) to observe the transition zone of the two regions, a region of 3C/4H overlapping growth below it was found. Bright areas corresponded to 3C, while dark areas corresponded to 4H, as confirmed by Raman spectroscopy and other SEM images. The growth interfaces of the two crystal types were clearly discernible and relatively compact. Furthermore, the growth angles of the two crystal types and their correlation with the cutting direction strongly suggest that this overlap is related to the formation of micro-nano steps on the substrate surface.

Development of an angle detection system for channeling implantation to the c-axis of SiC using birefringence phenomenon

We developed an angle detection system for channeling ion implantation in 4H-SiC using the birefringence phenomenon. Our optical method detects the c-axis direction in 4H-SiC due to its uniaxial optical properties. The system, consisting of a laser, polarizer, gonio stage, and analyzer, is simple and cost-effective. We conducted experiments on both on-axis and off-axis 4H-SiC (0001) samples, presenting angular dependence results around the [1–100] and [11–20] rotations. Despite the need for consideration of light incident angles, the performance was comparable to Rutherford backscattering spectrometry. These findings suggest the potential application of our system in channeling implantation to the c-axis of 4H-SiC.

Step flow growth of β-Ga2O3 films on off-axis 4H-SiC substrates by LPCVD

In this work, β-Ga2O3 films were prepared on 4H-SiC (0001) substrates with 4° off-axis by low-pressure chemical vapor deposition (LPCVD). The crystalline structures, chemical compositions, optical properties, and surface/interface of the as-prepared films and heterostructures were all comprehensively investigated. X-ray diffraction and room temperature Raman spectrometry demonstrated β-Ga2O3 films are pure phase with highly preferential growth orientation along the (-201) plane. The Ga/O ratio estimated by X-ray photoelectron spectroscopy was 0.7, indicating the existence of Ga-O bonding. In addition, β-Ga2O3 films showed high transmittance at wavelengths over 300 nm, corresponding to an optical bandgap of about 4.88 eV. Remarkably, the growth of β-Ga2O3 films on 4H-SiC substrates with 4° off-axis followed the step-flow growth mode, reported for the first time. The relevant growth mechanism was discussed. These results demonstrated the feasible formation of heteroepitaxial growth of β-Ga2O3 films with high crystal quality and superior electrical properties on 4H-SiC substrates with off-axis angle by LPCVD, promising for applications in Ga2O3 based high power and optoelectronic devices.

Polarity Control by Inversion Domain Suppression in N-Polar III-Nitride Heterostructures

Nitrogen-polar III-nitride heterostructures offer advantages over metal-polar structures in high frequency and high power applications. However, polarity control in III-nitrides is difficult to achieve as a result of unintentional polarity inversion domains (IDs). Herein, we present a comprehensive structural investigation with both atomic detail and thermodynamic analysis of the polarity evolution in low- and high-temperature AlN layers on on-axis and 4° off-axis carbon-face 4H-SiC (0001̅) grown by hot-wall metal organic chemical vapor deposition. A polarity control strategy has been developed by variation of thermodynamic Al supersaturation and substrate misorientation angle in order to achieve the desired growth mode and polarity. We demonstrate that IDs are completely suppressed for high-temperature AlN nucleation layers when a step-flow growth mode is achieved on the off-axis substrates. We employ this approach to demonstrate high quality N-polar epitaxial AlGaN/GaN/AlN heterostructures.

High quality epitaxial graphene on 4H-SiC by face-to-face growth in ultra-high vacuum

Epitaxial graphene on SiC is the most promising substrate for the next generation 2D electronics, due to the possibility to fabricate 2D heterostructures directly on it, opening the door to the use of all technological processes developed for silicon electronics. To obtain a suitable material for large scale applications, it is essential to achieve perfect control of size, quality, growth rate and thickness. Here we show that this control on epitaxial graphene can be achieved by exploiting the face-to-face annealing of SiC in ultra-high vacuum. With this method, Si atoms trapped in the narrow space between two SiC wafers at high temperatures contribute to the reduction of the Si sublimation rate, allowing to achieve smooth and virtually defect free single graphene layers. We analyse the products obtained on both on-axis and off-axis 4H-SiC substrates in a wide range of temperatures (1300 °C–1500 °C), determining the growth law with the help of x-ray photoelectron spectroscopy (XPS). Our epitaxial graphene on SiC has terrace widths up to 10 μm (on-axis) and 500 nm (off-axis) as demonstrated by atomic force microscopy and scanning tunnelling microscopy, while XPS and Raman spectroscopy confirm high purity and crystalline quality.

Effective Penetration Depths Investigation on Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in 4H-SiC Crystals through Ray-Tracing Simulation

The demand for power electronic devices fabricated from silicon carbide (SiC) has increased rapidly in recent years for a diverse range of existing and emerging applications. The development of device technology highly depends on the quality of substrate and epitaxial material and the number of deleterious defects within, as those are critical factors that impact the device performance and long-term reliability [1, 2]. Therefore, understanding the nature of defects is of great importance for preventing the degradation or premature breakdown of devices. Synchrotron X-ray topography (XRT) is a dominant analytical method for the imaging and characterization of crystallographic defects. For 4° off-axis (0001) 4H-SiC wafers, the grazing-incidence geometry topographic technique is commonly employed to focus on the defect investigation near surface region. In this geometry, a small incidence angles (~1-2°) is used for allowing X-ray to only penetrate the sample with a shallow depth below the surface, therefore, it is essential to establish a procedure to define the effective penetration depth for detailed analysis of dislocation structures and density calculations. In earlier studies, Dudley in 1989 concluded that the observed penetration depths are limited by photoelectric absorption rather than extinction [3]. Ishiji in 2017 estimated the penetration depth based on the photoelectric absorption experienced by the diffracted X-rays [4]. However, only basal plane dislocations (BPDs) with screw segments parallel to the off-cut [11-20]-direction were evaluated in that study, which is insufficient for evaluating other types of BPDs. Therefore, a universal method to determine the effective penetration depth for all dislocation types would be of more practical importance.In this study, a procedure to define this effective penetration depth is demonstrated by investigating physical vapor transport (PVT) grown 4° off-axis 4H-SiC crystals through preforming systematic analysis of topographic and ray-tracing simulated contrast of BPDs with different Burgers vector and line direction combinations. The topographic images are recorded through synchrotron monochromatic beam in grazing incidence geometry. The simulation model is based on the principle of orientation contrast mechanism [5, 6] and developed by considering both the effects of surface relaxation [7] and X-ray absorption [8, 9] for evaluating the contributed factors of dislocation contrast formation. Analysis of the results indicates the observable dislocation contrast depends on the effective misorientation associated with the dislocation modulated by the photoelectric absorption effect. The dislocations with larger effective misorientation are associated with longer projected lengths and corresponding deeper effective penetration depths. A more simplified factor based on an approximate expression for the misorientation is also introduced in this study as an alternative to the full ray-tracing simulation approach. The effective penetration depth determination method presented in this study enables three-dimensional dislocation configuration analysis and accurate density calculations.Reference: Das, H., et al., Materials Science Forum, 2019. 963: p. 284-287.Kimoto, T., et al. 2017 IEEE International Reliability Physics Symposium (IRPS). 2017.Dudley, M., J. Wu, and G.D. Yao, Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, 1989. 40-41: p. 388-392.Ishiji, K., et al., Japanese Journal of Applied Physics, 2017. 56(10): p. 106601.Dudley, M., X.R. Huang, and W. Huang, Journal of Physics D: Applied Physics, 1999. 32(10A): p. A139-A144.Huang, X.R., et al., Journal of Applied Crystallography, 1999. 32(3): p. 516-524.Peng, H., et al., Journal of Applied Crystallography, 2021. 54(2): p. 439-443.Fujie, F., et al., Acta Materialia, 2021. 208: p. 116746.Ailihumaer, T., et al., Materials Science and Engineering: B, 2021. 271: p. 115281. Figure 1

(Invited, Digital Presentation) Improved Reliability of 4H-SiC Metal-Oxide-Semiconductor Devices Utilising Atomic Layer Deposited Layers with Enhanced Interface Quality

A major component of reliability of Silicon Carbide (4H-SiC) power electronics are due to the gate dielectric. Specific aspects such as hysteresis, insulator lifetime, threshold voltage (VTH) instability and high leakage currents, remain an issue of paramount importance which hamper the uptake of 4H-SiC power MOSFETs.1 The oxide understood to have the most importance is coincidently the native oxide, SiO2, due to the suitable band offset to 4H-SiC. However, most of the SiO2/SiC interface problems, such as carbon clusters, H content and O vacancies, are directly related to the thermal oxidation process.2 Here, we show these issues can partially be avoided by using dielectric deposition instead.Atomic layer deposition (ALD) offers specific advantages such as very low deposition temperature, excellent process control and suitability for conformal deposition of gate oxides in trench structures.3 Deposited oxides still require a post-deposition anneal (PDA) in a nitrogen-containing ambient4 such as nitrous oxide (N2O) or nitric oxide (NO) [2] to passivate the defects within the stack and improve the as-deposited layer’s poor electrical quality. We present the excellent reliability performance of ALD-deposited SiO2 layers on SiC through fabrication of metal-oxide-semiconductor capacitors (MOSCAPs) and then using time-dependent dielectric breakdown (TDDB) characterisation. The distribution of interface parameters, as well as the results from TDDB, have been investigated as metrics of improvement following the N2O PDA process. For benchmarking, processes will be compared to thermally grown oxides4 and LPCVD-deposited dielectric layers to demonstrate the superior process quality.An active 10 µm thick epitaxial layer of 4 × 1015 cm-3 n-type doping is used in this study and grown on 100 mm diameter, 4° off-axis (0001) 4H-SiC wafers. Growth was performed using a 30 μm/hr growth and N2 as a dopant in an LPE ACiS M8 chemical vapour deposition (CVD) reactor. After an initial clean, a 1 µm thick field oxide was deposited and a window was opened via photolithography and reactive ion etching (RIE). Then, quarter wafers underwent one of the three oxidation routines: 1. SiO2 plasma deposition at 200 °C using bis(diethylamino)silane (BDEAS) and O2 plasma precursors in an Ultratech Fiji G2 Plasma-Enhanced ALD System. 2. SiO2 deposition at 750 °C using tetraethyl orthosilicate (TEOS) as a precursor in a Thermco LPCVD system. 3. direct thermal growth of SiO2 in a HiTech furnace at 1300 °C for 5 hrs in N2O ambient. Samples that had undergone one of the first two routines then underwent a PDA in N2O, in the HiTech furnace at 1300°C for 2 hrs. All oxidation measurements resulted in oxide thicknesses between 50 and 60 nm, which were verified using step-height AFM measurements and optical interferometry. To create the vertical MOSCAP structure samples had a 500 nm aluminium (Al) backside contact deposited, before a 1 μm Al layer was deposited on the topside of the samples by means of a liftoff process. A cross-sectional diagram of the fabricated final device structure is shown in Fig. 1 (a). Table I shows the key electrical parameters which were extracted using room temperature C-V measurements, combined with I-V and constant field TDDB measurements at 175 °C. Fig. 1 (b) shows the improvement brought about by the N2O anneal, which also results in the average flatband voltage being reduced by more than 10 V to the lowest value of the dataset (1.44 V) and frequency dispersion mostly removed, with all but the ALD as-deposited samples reaching average breakdown oxide fields of about 10 MV/cm. The most promising improvement of the ALD-deposited SiO2 can be seen observing the breakdown distribution of MOSCAPs when stressed at constant high electric field (9 MV/cm), which can be seen in Fig. 2 (a) and (b). Here, these samples reach a TDDB, 63% value of 4786 s, which represents an average increase of 28% when compared to LPCVD samples and 58% when comparing this to a purely thermal process.Further evidence will be presented that high-quality, high-reliability SiO2 layers, formed by ALD and PDA have been formed. Flatband voltage and hysteresis are reduced, compared to thermally grown oxide, and frequency dispersion in accumulation is negligible. The ALD oxide with PDA has higher reliability than LPCVD and thermal oxides in TDDB tests, offering 29% to 345% improvement. The degradation mechanisms of the ALD oxide are different to that the LPCVD and thermal oxides and will be discussed in this talk.[1] P. Moens et al, ISPSD 32, 78-71 (2020).[2] P. Fiorenza et al, Appl. Surf. Sci., 149752 (2021).[3] A. Renz et al, MSSP 122, 105527 (2021).[4] K. Tachiki et al, Appl. Phy. Expr. 13.12, 121002(2020). Figure 1

Strain Release in GaN Epitaxy on 4° Off-Axis 4H-SiC.

A hybrid field-effect transistor (HyFET), superior for power electronic applications, can be created by harnessing the merits of two representative wide-bandgap semiconductors, gallium nitride (GaN) and silicon carbide (SiC). Yet, the incompactness in the epitaxy techniques hinders the development of the HyFET-GaN is usually grown on on-axis foreign substrates including SiC, whereas SiC homoepitaxy prefers off-axis substrates. This work presents a GaN-based heterostructure epitaxially grown on a conventional 4° off-axis 4H-SiC substrate, which manifests its high quality and suitability for constructing GaN-based high-electron-mobility transistors, thereby suggesting a practical approach to realizing HyFETs. In the meanwhile, a distinct two-step biaxial strain-relaxation process is proposed and studied with comprehensive characterizations.

Atomic layer deposition of AlN on different SiC surfaces

Thin AlN films were grown using a Picosun R-200 atomic layer deposition (ALD) reactor on SiC surfaces with different crystallographic orientation: on-axis 4H-SiC (0001) and 8° off-axis 4H-SiC. TMA (trimethylaluminium) and NH3 were used as precursors while hydrogen and nitrogen plasma were applied for in-situ substrate cleaning. The substrate temperatures were 400 °C and 450 °C, with 20 ALD cycles. The surface morphology was investigated by scanning electron microscopy (SEM), which revealed nanometer-sized islands in all films. The AlN films deposited on on-axis 4H-SiC at 450 °C substrate temperature exhibited a relatively small roughness of about 0.255 nm. The chemical composition and bonding states were investigated by X-ray photoelectron spectroscopy. For all layers, high-resolution XPS showed Al 2p and N 1s spectra that are characteristic of AlN. These results are a good prerequisite of establishing the growth conditions of AlN films for surface acoustic wave (SAW) devices.

Analysis of Dislocation Contrast in Synchrotron Grazing-incidence X-ray Topographs and Ray-tracing Simulation in Off-axis 4H-SiC Crystals

The contrast of dislocations lying on the basal plane in off-axis 4H-SiC crystals, such as basal plane dislocations, deflected threading screw and mixed dislocations are simulated using a more sophisticated ray-tracing simulation method, which is based on the orientation contrast mechanism. The effects of surface relaxation combined with X-ray absorption are both considered in this simulation method in order to further evaluate the factors contributing to the dislocation contrast formation. Comparison of the simulated results with the actual grazing-incidence topographic images of the dislocations reveals that the dislocation contrast is dominated by surface relaxation effect, which mainly occurs for diffractions near the crystal surface. Depth analysis shows that the diffracted X-ray beam from regions below the dislocation contribute additional contrast to the image formation. With consideration of X-ray absorption, the simulated contrast of the dislocation gradually weakens as the diffraction position gets deeper into the crystal. Detailed discussion on each type of dislocation on the basal plane including inclined dislocation contrast is presented in this paper. The full BPD loop contrast is also simulated and thus the Burgers vectors of all types of BPDs can be determined by comparing with the simulated results.

Analysis of Dislocation Contrast in Synchrotron Grazing-incidence X-ray Topographs and Ray-tracing Simulation in Off-axis 4H-SiC Crystals

A sophisticated simulation model is developed based on the principle of ray-tracing to simulate the grazing-incidence synchrotron X-ray topographic contrast of dislocations lying on the basal plane including basal plane dislocations and deflected threading screw and mixed dislocations in off-axis 4H-SiC crystals. The model incorporates effects of surface relaxation as well as the photoelectric absorption to predict dislocation contrast. Compared to conventional ray-tracing images, surface relaxation effects dominate dislocation contrast for diffraction near the crystal surface. The simulated dislocation contrast gradually weakens with increasing depth of the diffracted beam position within the crystal due to photoelectric absorption. The distinctive features of the net simulated dislocation images obtained by aggregating through the effective penetration depth correlate well with contrast features observed on the experimental topographic images. Depth analysis reveals that in some cases the diffracted X-rays from regions below the dislocation can contribute additional contrast features previously not considered.

Surface relaxation and photoelectric absorption effects on synchrotron X-ray topographic images of dislocations lying on the basal plane in off-axis 4H-SiC crystals

A more sophisticated simulation model is developed based on the principle of ray-tracing to simulate the grazing-incidence synchrotron X-ray topographic contrast of dislocations lying on the basal plane including basal plane dislocations and deflected threading screw and mixed dislocations in off-axis 4H-SiC crystals. The model incorporates effects of surface relaxation as well as the photoelectric absorption to predict dislocation contrast. Compared to conventional ray-tracing images, surface relaxation effects dominate dislocation contrast for diffraction near the crystal surface. The simulated dislocation contrast gradually weakens with increasing depth of the diffracted beam position within the crystal due to photoelectric absorption. The distinctive features of the net simulated dislocation images obtained by aggregating through the effective penetration depth correlate well with contrast features observed on the experimental topographic images. Depth analysis reveals that in some cases the diffracted X-rays from regions below the dislocation can contribute additional contrast features previously not considered.

Effects of annealing on the interfacial properties and energy-band alignment of AlN dielectric on 4H–SiC

Interfacial properties and energy-band alignment of annealed AlN dielectric films on Si-face 4° off-axis 4H–SiC substrates were characterized and demonstrated by x-ray photoelectron spectroscopy (XPS) and current-electric field (I–E) measurements. The XPS results reveal that the Al–O bonds and the silicon suboxides can convert into more stable Al–N bonds and Al–O–Si bonds at the AlN/4H–SiC interface under 1000 °C annealing. The variations in both oxygen-rich composition and the crystallinity in AlN make annealing-dependent conduction band offsets of as-deposited and annealed AlN/4H–SiC to be 1.36 eV and 1.20 eV, respectively. Meanwhile, I–E measurements separately yield the occurrence of the Fowler–Nordheim (FN) tunneling and space-charge-limited conduction in as-deposited and annealed metal-insulator-semiconductor capacitors, corresponding to lower barrier heights of 0.92 eV and 0.54 eV, respectively. The reason for the energy-band shift between I–E derivations and the XPS results was analyzed and demonstrated together. These results can provide considerable insight into the energy-band alignment of AlN as gate dielectric or passivation layers on 4H–SiC based devices.

Low-temperature epitaxial Si on 4H-SiC using metal-induced crystallization

Metal induced crystallization using aluminum (Al) as catalytic metal was applied to achieve low-temperature crystallization of amorphous silicon (a-Si) on 4H-SiC. Epitaxial crystallization of Si grains was found to occur on off-axis 4H-SiC at very low temperatures using X-ray diffractometry (XRD). In-situ heating XRD measurements revealed an onset of the crystallization process at temperatures as low as 220 °C on Si- and C-face SiC, respectively. Cross-sectional imaging with scanning electron microscopy showed an almost complete layer transfer between Si and the Al metallization after annealing.