Octagonal Gate Research Articles

The Influence of Back Gate Bias on the OCTO SOI MOSFET’s Response to X-ray Radiation

This work investigates the X-ray irradiation impact on the performance of an on-conventional transistor called OCTO SOI MOSFET that adopts an octagonal gate shape instead of a rectangular. The electrical behaviors of both devices were studied through an experimental comparative analysis of the total ionizing dose influence. In addition, the back-gate bias technique was applied in these devices to reestablish its threshold voltages and drain currents conditions that were degraded due the trapping of positive charges in the buried oxide. As the main finding of this work, after the irradiation procedure, we notice that the OCTO device is capable to reestablish its pre-rad electrical behavior with a smaller back gate bias than the one observed in the standard one counterpart. This is mainly because the parasitic transistors in the bird’s beak region are practically deactivated due the particular octagonal gate geometry.

Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays Total Ionizing Doses (TIDs), under the on-state bias conditions. The results indicate that the Octo layout style with alpha ( $\alpha $ ) angle equal to 90° and a cut factor of 50% for MOSFETs is capable of boosting the device matching by at least 56.1%, on average, regarding the electrical parameters studied (Threshold Voltage and Subthreshold Swing), as compared to those found in the Conventional MOSFET counterparts, considering that they present the same bias conditions and regarding different TIDs. This happens due to the Longitudinal Corner Effect (LCE), Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) which are present in the Octo MOSFETs. Therefore, the Octagonal layout style can be considered as an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS ICs applications.

Using a Non-Conventional Layout Style to Improve Pass Device Performance in CL-LDO Voltage Regulators

Currently the need for solutions on a single integrated circuit (IC) focusing on mobile applications (using batteries), more compact with less power consumption, such as mobile phones, tablets, notebooks, data collectors, etc., has become almost mandatory. This approach establishes the electronic systems integrated into a single IC, System-On-Chip (SoC). Accordingly, the integration of power management circuits (Power Management Unit – PMU), such as voltage regulators, which are responsible for feeding with fixed voltage different blocks of a SoC with a large electric current load range. This type of IC has been the focus of much research, aiming to increase its electrical performance and reducing its dimensions. Among the different architectures of linear regulators, linear voltage regulator with no external capacitor and low dropout voltage (Capacitor Less Low Dropout – CL-LDO) has been used widely. One of the key elements of CL-LDO is the pass device MOSFET, which is responsible for providing the supply reference voltage of the hole circuits, independent of the maximum load current. Accordingly, the pass device occupies a large silicon area, which finishes limiting the total area of the linear regulator, even using the minimal technology length. In this context, the objective of this paper is present results from a comparison between two identical CL-LDO voltage regulators, one using a conventional geometry pass device MOSFETs and the other one an octagonal layout style geometry, in SiGe IBM 130nm. By occupying the same layout area (0.00994mm2), the regulator using the non-conventional layout style in the pass device improved significant results in a large range of test possibilities by using physical effects due to the octagonal gate geometry. This kind of approach in back-end analog design flow is quite simple, and doesn't occupy any additional area for the IC, bringing a lot of benefits like higher transconductance and lower on resistance. Considering a 3-sigma process variance, military temperature range, maximum load of 20mA and the input voltage between 1.5V and 2.5V, the conventional layout results in a quiescent current of 30.5585 ± 2.08626µA against 30.5577 ± 2.05037µA from octagonal layout, improving static power consumption. Had also improved power-supply rejection ratio (PSRR) at low frequencies, from -55.76 ± 5.701dB (DC) to -55.78 ± 3.833dB (DC) and PSRR at high frequencies, from -48.81 ± 6.242dB (10kHz) to -48.81 ± 4.905dB (10kHz), maintaining line regulation and load regulation in order of 1,83%/V and 0,083%/mA respectively, for both voltage regulators with different pass device layout styles. With all the results, it is possible to conclude that, by using a non-conventional layout style, the MOSFET shows less yield variation, even with a short channel design, improving mismatch and the final results of a LDO voltage regulator. Figure 1

Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment

This paper describes an experimental comparative study between the silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field effect transistors (MOSFETs) implemented with the octagonal gate geometries and their typical rectangular counterparts operating in high-temperature conditions. The 1 ${\mu }\text{m}$ fully depleted SOI complementary metal-oxide semiconductor technology was employed to manufacture the devices. We observe that the octagonal layout style for MOSFETs is capable of maintaining its better electrical performance (for 573 K: a reduction of the leakage drain current of 65%, an increase of 159% in the saturation drain current, and an increase of 175% in the unit voltage gain frequency) in comparison to the standard rectangular counterpart. This happens because the longitudinal corner effect and parallel connection of MOSFETs with different channel lengths effect continue to function at high temperatures. Therefore, the octagonal layout style can be considered as an alternative hardness-by-design approach to boost the electrical performance of n-type SOI MOSFETs in high-temperature environments, without causing any extra burden for any current planar SOI MOSFET manufacturing process.

Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET

This paper performs an experimental comparative study of the total ionizing dose effects due to the x-ray radiation between the silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) manufactured with octagonal gate geometry and the standard counterpart. Our main focus is on integrated transceivers for wireless communications and smart-power dc/dc converters for mobile electronics, where the transistor is used as the key switching element. It is shown that this innovative layout can reduce the total ionizing dose (TID) effects due to the special characteristics of the OCTO SOI MOSFET bird’s beak regions, where longitudinal electrical field lines in these regions are not parallel to the drain and source regions. Consequently, the parasitic MOSFETs associated with these regions are practically deactivated.

Experimental Study of the OCTO SOI nMOSFET and Its Application in Analog Integrated Circuits

This paper presents an experimental comparative study between the OCTO, Diamond and Conventional Silicon-On-Insulator nMOSFETs (OSM, DSM and CSM, respectively), considering the same bias condition for all devices. The first comparison between the OSM and the CSM counterpart considers the same gate area and the second between the OSM and DSM regards the same geometric factor, in order to verify the benefits of the octagonal gate geometry, that uses the longitudinal corner effect to increase the resultant longitudinal electric field along of the channel, to improve the device performance and consequently to enhance the performance of analog integrated circuits. These characteristics can be observed on the main analog parameters such as drain current in saturation region, maximum transconductance, transconductance by drain current, voltage gain, unity voltage gain frequency and Early voltage.

Simulation and analysis of the frequency performance of a new silicon nanowire MOSFET structure

In this work we used a three-dimensional quantum mechanical simulation approach to simulate a silicon nanowire MOSFET with square cross section. Different gate structures such as double-gate and gate-all-around with a square gate around the wire (square gate-all-around) and with an octagonal gate around the wire (octagonal gate-all-around) are investigated. The Poisson and the Schrödinger equations are solved self-consistently in this analysis. For solving the Poisson equation the Newton–Raphson method and for solving the Schrödinger equation the non-equilibrium Green's function approach are used. By this simulator the drain current and the electron density and their variations versus the gate voltage are obtained. The transconductance (gm), the gate capacitance (CG) and then the cut-off frequency (fT) are calculated. The short channel effects (i.e. the subthreshold slope and the drain off-current) versus variation of the silicon thickness are obtained. We compared gm, CG and fT for different structures of silicon nanowire MOSFET, i.e. the double-gate, the square gate-all-around and the octagonal gate-all-around due to variation of the gate voltage, the oxide thickness and the silicon thickness. Some advantages for the proposed gate-all-around structure over the other structures are observed.

3D quantum mechanical simulation of square nanowire MOSFETs by using NEGF method

Abstract In order to investigate the specifications of nanoscale transistors, we have used a three dimensional (3D) quantum mechanical approach to simulate square cross section silicon nanowire (SNW) MOSFETs. A three dimensional simulation of silicon nanowire MOSFET based on self consistent solution of Poisson-Schrödinger equations is implemented. The quantum mechanical transport model of this work uses the non-equilibrium Green’s function (NEGF) formalism. First, we simulate a double-gate (DG) silicon nanowire MOSFET and compare the results with those obtained from nanoMOS simulation. We understand that when the transverse dimension of a DG nanowire is reduced to a few nanometers, quantum confinement in that direction becomes important and 3D Schrödinger equation must be solved. Second, we simulate gate-all-around (GAA) silicon nanowire MOSFETs with different shapes of gate. We have investigated GAA-SNW-MOSFET with an octagonal gate around the wire and found out it is more suitable than a conventional GAA MOSFET for its more I on/I off, less Drain-Induced-Barrier-Lowering (DIBL) and less subthreshold slope.

Planar Power MOSFETs for Smart Power CMOS Switches

Planar power MOSFETs with an octagonal gate are designed, fabricated, and tested. The implantation dose of the pinch-resistor region is optimized for off-state breakdown voltage times on-state resistance by computer simulation.