Using a Non-Conventional Layout Style to Improve Pass Device Performance in CL-LDO Voltage Regulators

Abstract

Currently the need for solutions on a single integrated circuit (IC) focusing on mobile applications (using batteries), more compact with less power consumption, such as mobile phones, tablets, notebooks, data collectors, etc., has become almost mandatory. This approach establishes the electronic systems integrated into a single IC, System-On-Chip (SoC). Accordingly, the integration of power management circuits (Power Management Unit – PMU), such as voltage regulators, which are responsible for feeding with fixed voltage different blocks of a SoC with a large electric current load range. This type of IC has been the focus of much research, aiming to increase its electrical performance and reducing its dimensions. Among the different architectures of linear regulators, linear voltage regulator with no external capacitor and low dropout voltage (Capacitor Less Low Dropout – CL-LDO) has been used widely. One of the key elements of CL-LDO is the pass device MOSFET, which is responsible for providing the supply reference voltage of the hole circuits, independent of the maximum load current. Accordingly, the pass device occupies a large silicon area, which finishes limiting the total area of the linear regulator, even using the minimal technology length. In this context, the objective of this paper is present results from a comparison between two identical CL-LDO voltage regulators, one using a conventional geometry pass device MOSFETs and the other one an octagonal layout style geometry, in SiGe IBM 130nm. By occupying the same layout area (0.00994mm2), the regulator using the non-conventional layout style in the pass device improved significant results in a large range of test possibilities by using physical effects due to the octagonal gate geometry. This kind of approach in back-end analog design flow is quite simple, and doesn't occupy any additional area for the IC, bringing a lot of benefits like higher transconductance and lower on resistance. Considering a 3-sigma process variance, military temperature range, maximum load of 20mA and the input voltage between 1.5V and 2.5V, the conventional layout results in a quiescent current of 30.5585 ± 2.08626µA against 30.5577 ± 2.05037µA from octagonal layout, improving static power consumption. Had also improved power-supply rejection ratio (PSRR) at low frequencies, from -55.76 ± 5.701dB (DC) to -55.78 ± 3.833dB (DC) and PSRR at high frequencies, from -48.81 ± 6.242dB (10kHz) to -48.81 ± 4.905dB (10kHz), maintaining line regulation and load regulation in order of 1,83%/V and 0,083%/mA respectively, for both voltage regulators with different pass device layout styles. With all the results, it is possible to conclude that, by using a non-conventional layout style, the MOSFET shows less yield variation, even with a short channel design, improving mismatch and the final results of a LDO voltage regulator. Figure 1