NW Tr Research Articles

Comprehensive study of variability in poly-Si channel nanowire transistor

Variability in poly-Si nanowire transistors (NW Tr.) is studied with respect to device and grain size. Threshold voltage (Vth) variability decreases as grain size or NW width (W) decreases since the number of grain boundaries in carrier passage increases. Drain current (Id) variability shows similar grain size and W dependences, while Id variability in short channel Tr. is suppressed due to the parasitic resistance. In addition, Id variability decreases with high lateral or perpendicular electric field as well as high temperature due to potential barrier lowering at grain boundaries.

Experimental study of time-dependent dielectric breakdown in tri-gate nanowire transistor

We systematically investigate the size dependence of the time-dependent dielectric breakdown (TDDB) in a tri-gate nanowire transistor (NW Tr.). It is newly found that TDDB reliability is degraded in NW Tr. as compared with that in a planar transistor owing to the locally enhanced electric field at the NW corner. Moreover, in the region with a width (W) less than 40 nm, nanowire width reduction leads to a shorter time to gate dielectric breakdown indicating additional degradation of TDDB reliability in NW Tr. with smaller W. Although TDDB in three-dimensional (3D) MOS structures such as a trench MOS capacitor has already been reported, the size dependence of TDDB in scaled NW Tr. is firstly discussed in this paper since a trench capacitor is different from recent NW Tr. in structure, device size, gate dielectric thickness, and scaling effect on TDDB.

BSIM4 parameter extraction for tri-gate Si nanowire transistors

We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes. SPICE modeling tool was used to extract the parameter from Id–Vg to Id–Vd characteristics with liner and saturation region. Dependence of source/drain parasitic resistances on nanowire width and gate sidewall thickness can be observed on the extracted parameters. Furthermore, parasitic capacitance was extracted from three-dimensional TCAD simulation with our fabricated device structure. Single sets of parameters can reproduce I–V characteristics with Lg down to 35nm for n-channel nanowire transistors. It was found that the extracted parameters will be a useful tool for characterizing the circuit performance of nanowire transistor. Therefore, this procedure is applicable to extract the BSIM4 model parameters for NW Tr. as well as other multi-gate FETs.

Experimental Study of Random Telegraph Noise in Trigate Nanowire MOSFETs

Random telegraph noise (RTN) in trigate nanowire transistors (NW Tr.) is systematically studied with respect to the NW size dependence. Time to capture and emission, which is related to the characteristic of the traps, such as trap energy, is independent of NW size. On the other hand, noise amplitude increases as the NW size decreases showing the similar size dependence to the reported scaled planar Tr. In addition, RTN after hot-carrier injection (HCI) and negative bias stress (NBS) is studied. HCI and NBS induce additional carrier traps, which generate larger noise signals. Since the degradation by HCI or NBS is larger with narrower width, RTN after these stresses is found to be severer in the NW Tr.

Channel size dependence of low-frequency noise in tri-gate silicon nanowire transistors

We systematically study the channel size dependence of drain current noise amplitude in tri-gate silicon nanowire transistors (NW Tr.) by measuring a large number of samples with various parameters such as gate length (Lg), NW width (WNW), and NW height (HNW) down to 10 nm. The noise of NW Tr. with WNW < 20 nm rapidly increases with 1/WNW because an electron in a single trap on the NW channel blocks the entire current flow (bottleneck effects). The strength of bottleneck effects is determined solely by WNW not by HNW. The noise increase at narrow WNW is smaller in short-Lg Tr. (down to 15 nm).

SPICE-Based Performance Analysis of Trigate Silicon Nanowire CMOS Circuits

An ultralow-voltage performance is investigated in nanowire transistors (NW Tr.) CMOS circuits. SPICE model parameters of BSIM4 are extracted from measurement data of NW Tr. fabricated on 300-mm SOI wafer. The delay time and the power consumption are examined between nanowire and bulk-Si CMOS circuits. The operation voltage of a nanowire CMOS inverter with an ideal subthreshold slope can be reduced by 300 mV from that of the bulk-Si CMOS inverter. NW-Tr.-based circuits under voltage scaling have immunity from supplying voltage fluctuation and suppression of operation delay variation.