Numerically Controlled Oscillator Research Articles

Design and memory optimization of hybrid gate diffusion input numerical controlled oscillator

The numerically controlled oscillator (NCO) is one of the digital oscillator signal generators. It can generate the clocked, synchronous, discrete waveform, and generally sinusoidal. Often NCOs care utilized in the combinations of digital to analog converter (DAC) at the outputs for creating direct digital synthesizer (DDS). The network on chips (NOCs) are utilized in various communication systems that are fully digital or mixed signals such as synthesis of arbitrary wave, precise control for sonar systems or phased array radar, digital down/up converters, all the digital phase locked loops (PLLs) for cellular and personal communication system (PCS) base stations and drivers for acoustic or optical transmissions and multilevel phase shift keying/frequency shift keying (PSK/FSK) modulators or demodulators (modem). The basic architecture of NCO will be enhanced and improved with less hardware for facilitating complete system level support to various sorts of modulation with minimum FPGA resources. In this paper design and memory optimization of hybrid gate diffusion input (GDI) numerically controlled oscillator based on field programmable gate array (FPGA) is implemented. compared with NCO based 8-bit microchip, memory optimization of hybrid GDI numerically controlled oscillator based on FPGA gives effective outcome in terms of delay, metal-oxide-semiconductor field-effect transistors (MOSFET’s) and nodes.

Research and Implementation of a Numerical Control Oscillator with Improved Pipelined CORDIC Algorithm

As the recognized core of electronic systems, frequency synthesizers have been applied in many communication fields. NC oscillator (NCO) is the main component of the frequency synthesizer. It helps to generate high-precision and high-frequency signals, so it has been widely used. NCO implementation methods include table lookup method, polynomial expansion method, coordinate rotation digital computer (CORDIC) algorithm, etc. CORDIC algorithm is one of many commonly used methods in trigonometric function calculation and digital signal processing, and is often used as the core of DDS (direct digital synthesis) to generate signals. Compared with table lookup and polynomial expansion, CORDIC algorithm has higher efficiency in signal generation and hardware utilization. In view of the disadvantages of traditional CORDIC algorithm, which takes up large resources and has relatively slow calculation speed, in order to improve the output efficiency, this paper uses an efficient 12-stage pipelined CORDIC architecture and a very small lookup table (LUT) to implement a sine wave generator. The system is coded and simulated in Quartus and ModelSim. The results show that the proposed structure can increase the operating speed of the system from 217.77 MHz to 291.04 MHz, and improve the output efficiency of the system.

High-Accuracy Absolute-Position-Aided Code Phase Tracking Based on RTK/INS Deep Integration in Challenging Static Scenarios

Many multi-sensor navigation systems urgently demand accurate positioning initialization from global navigation satellite systems (GNSSs) in challenging static scenarios. However, ground blockages against line-of-sight (LOS) signal reception make it difficult for GNSS users. Steering local codes in GNSS basebands is a desirable way to correct instantaneous signal phase misalignment, efficiently gathering useful signal power and increasing positioning accuracy. Inertial navigation systems (INSs) have been used as effective complementary dead reckoning (DR) sensors for GNSS receivers in kinematic scenarios, resisting various forms of interference. However, little work has focused on whether INSs can improve GNSS receivers in static scenarios. Thus, this paper proposes an enhanced navigation system deeply integrated with low-cost INS solutions and GNSS high-accuracy carrier-based positioning. First, an absolute code phase is predicted from base station information and integrated solutions of the INS DR and real-time kinematic (RTK) results through an extended Kalman filter (EKF). Then, a numerically controlled oscillator (NCO) leverages the predicted code phase to improve the alignment between instantaneous local code phases and received ones. The proposed algorithm is realized in a vector-tracking GNSS software-defined radio (SDR). Results of the time-of-arrival (TOA) and positioning based on real-world experiments demonstrated the proposed SDR.

Design and analysis of dual-mode numerically controlled oscillators based controlled oscillator frequency modulation

In this paper, the design and analysis of dual-mode numerically controlled oscillators (NCO) based controlled oscillator frequency Modulation is implemented. Initially, input is given to the analog to digital (ADC) converter. This will change the input from analog to digital converter. After that, the pulse skipping mode (PSM) logic and proportional integral (PI) are applied to the converted data. After applying PSM logic, data is directly transferred to the connection block. The proportional and integral block will transfer the data will be decoded using the decoder. After decoding the values, it is saved using a modulo accumulator. After that, it is converted from one hot residue (OHR) to binary converter. The converted data is saved in the register. Now both data will pass through the gate driver circuit and output will be obtained finally. From simulation results, it can observe that the usage of metal oxide semiconductor field effect transistors (MOSFETs) and total nodes are very less in dual-mode NCO-based controlled oscillator frequency modulation.

Datasets design of gate diffusion input based pipeline architecture for numerically controlled oscillator

<span lang="EN-US">Gate diffusion input (GDI) is a technique, which enables reducing power consumption, area and delay in the digital circuits significantly, at the same time maintains low complexity of the logical design. This paper focuses on the analysis and interpretation of the design and implementation of GDI-based pipeline architecture for numerically controlled oscillator (NCO) using look up table (LUT). Based on the input signal and the alternate signal, this phase separation will separate the phase difference signal. The NCO generates a frequency and phase harmonized output signal with an antecedence fixed frequency clock. The 32-bit counter then compares the current count to the value stored in the compare register. Here the Coherent control comes into picture. It controls the carrier synchronizer by employing data from the 32-bit counter and the obtained data will be saved. It is updated and advanced using the third peer group of frequency synthesis technology. The test outcomes are accompanied with the theoretical concept and reproduced the results. The main objective of GDI-based pipeline architecture for NCO using LUT is to reduce the usage of metal oxide semiconductor field effect transistors (MOSFET’s). NCO is an indispensable component in many digital communication systems linked to modems, software-defined radios, and digital radio, digital down/upconverters for cellular and personal communications service base stations.</span>

Design and Implementation of Vector Tracking Loop for High-Dynamic GNSS ReceiverDesign and Implementation of Vector Tracking Loop for High-Dynamic GNSS Receiver.

For the tracking of high-dynamic satellite navigation signals, the conventional scalar tracking loop (STL) is vulnerable. Frequent signal-tracking interruption affects the continuity of navigation. The vector tracking loop (VTL) can overcome this disadvantage. However, there are some difficulties in implementing existing vector tracking methods on a real-time hardware receiver, such as the synchronization problem and computation load. This paper proposes an implementation framework of VTL based on a partial open-loop numerically controlled oscillator (NCO) control mode that can be implemented with minor modifications on an existing receiver platform. The structure of VTL, the design of the navigation filter, and the key points of hardware implementation are introduced in detail. Lastly, the VTL performance was verified by a GPS simulator test. The results show that the proposed VTL can run in real-time and be significantly improved in the tracking continuity of high-dynamic signals, tracking sensitivity, positioning accuracy, and recovery time for interrupted signals compared with those of STL.

FPGA Implementation of an NCO Based CDR for the JUNO Front-End Electronics

This article describes a design of an field-programmable gate array (FPGA) implementation of a clock and data recovery (CDR) system. The core will be integrated in the FPGA configuration for the front-end electronics (FEE) board of the Jiangmen underground neutrino observatory (JUNO) experiment. The front-end will be placed on the main detector, underground and underwater, making the electronics not accessible after installation. The timing and trigger system relies on a synchronous link connection over CAT5e cable (up to 100 m long) between the front-end and the back-end electronics (BEE), where a twisted-pair is dedicated to clock-forwarding. The robustness of the recovery clock system is essential for the stability of the FPGA firmware. The proposed project is intended to improve the clock recovery operation by increasing the immunity of the link to sudden electromagnetic interference (EMI). On top of this, the core allows to free a twisted-pair in the link, since the clock can be recovered from the data and there is no more need for a clock-dedicated transmission. This will optimize the link granting the possibility to implement other features. The design is based on two components: a numerically-controlled oscillator (NCO), in order to create a controlled frequency clock signal, and a digital phase detector (PD) to match the clock frequency with the data rate. NCOs are often coupled with a digital-to-analog converter (DAC) to create direct digital synthesizers (DDSs), which are able to produce analog waveforms of any desired frequency. In the presented case instead, the NCO generates a digital clock signal of an arbitrary frequency, while the PD manages this frequency by intercepting any shifting on the relative phase between the clock and the data. A phase aligner (PA) module guarantees that data are sampled in the middle of the eye pattern, which represents the optimal sampling point. The article presents an overview of the NCO-based CDR design and implementation, together with some tests and results in order to verify the CDR reliability. Moreover, in the last section, some other possible applications of the core are illustrated.

Design and Validation of a Cascading Vector Tracking Loop in High Dynamic Environments

This paper designs a cascading vector tracking loop based on the Unscented Kalman Filter (UKF) for high dynamic environment. Constant improvement in dynamic performance is an enormous challenge to the traditional receiver. Due to the doppler effect, the satellite signals received by these vehicles contain fast changing doppler frequency shifts and the first and second derivatives of doppler frequency, which will directly cause a negative impact on the receiver’s stable tracking of the signals. In order to guarantee the dynamic performance and the tracking accuracy, this paper designs a vector carrier structure to estimate the doppler component of a signal. Firstly, after the coherence integral, the IQ values are reorganized into new observations. Secondly, the phase error and frequency of the carrier are estimated through the pre-filter. Then, the pseudorange and carrier frequency are used as the observations of the main filter to estimate the motion state of the aircraft. Finally, the current state is fed back to the carrier Numerical Controlled Oscillator (NCO) as a complete closed loop. In the whole structure, the cascading vector loop replaces the original carrier tracking loop, and the stable signal tracking of code loop is guaranteed by carrier assisted pseudo-code method. In this paper, with the high dynamic signals generated by the GNSS signal simulator, this designed algorithm is validated by a software receiver. The results show that this loop has a wider dynamic tracking range and lower tracking error than the second-order frequency locked loop assisted third-order phase locked loop in high dynamic circumstances. When the acceleration of carrier is 100 g, the convergence time of vector structure is about 100 ms, and the carrier phase error is lower than 0.6 mm.

Support Vector Machine Assisted GPS Navigation in Limited Satellite Visibility

This paper investigates performance improvement via the incorporation of the support vector machine (SVM) into the vector tracking loop (VTL) for the Global Positioning System (GPS) in limited satellite visibility. Unlike the traditional scalar tracking loop (STL), the tracking and navigation modules in the VTL are not independent anymore since the user’s position can be determined by using the information from other satellites and can be predicted on the basis of the states of the user. The method proposed in this paper makes use of the SVM to bridge the GPS signal and prevent the error growth due to signal outage. Similar to the neural network, the SVM is motivated by its ability to approximate an unknown nonlinear input-output mapping through supervised training. The SVM is employed for predicting adequate numerical control oscillator (NCO) inputs, i.e., providing better prediction of residuals for the Doppler frequency and code phase in order to maintain regular operation of the navigation system. When the navigation processing is in good condition, the SVM is at the training stage, and the output information from the discriminator and navigation filter is adopted as the inputs. Other machine learning (ML) algorithms such as the radial basis function neural network (RBFNN) and the Adaptive Network-Based Fuzzy Inference System (ANFIS) are employed for comparison. Performance evaluation for the SVM assisted architecture as compared to the RBFNN- and ANFIS-assisted methods and the un-assisted VTL will be carried out and the performance evaluation during GPS signal outage will be presented. The proposed design is very useful for navigation during the environment of limited satellite visibility to effectively overcome the problem in the environment of GPS outage.

A survey of digital down converter architecture for next generation wireless applications

This article presents a brief survey of Digital down Converter (DDC) architecture and its extensive applications. The distinctive feature of the DDC architecture is its frequency translation from real data signal at an intermediate frequency to a complex baseband signal at zero frequency. The architecture of DDC comprises of Numerically Controlled Oscillator (NCO) and decimation filters. The components of ultra efficient DDC architecture have been implemented in Field Programmable Gate Array (FPGA) device. This down converter provides high malleability, customizability and bearable cost. Due to its amenities, digital down converter was utterly studied and applied in many wireless communication technologies.

A Parallel Timing Synchronization Structure in Real-Time High Transmission Capacity Wireless Communication Systems

In the past few years, parallel digital signal processing (PDSP) architectures have been intensively studied to fulfill the growing demand of channel capacity in coherent optical communication systems. However, to our knowledge, real-time timing synchronization in such architectures is until now not implemented on a Field Programmable Gate Array (FPGA). In this article, a parallel timing synchronization architecture is proposed. In the architecture, a parallel First In First Out (FIFO) structure based on an index associated rearranging method, and a dual feedback loop based on the Gardner’s algorithm, are adopted. Taking advantages of the FIFO structure, 67% Look Up Table (LUT) is saved in comparison with earlier results, meanwhile the Numerically Controlled Oscillator (NCO) is efficiently improved to meet the FPGA timing requirements for real-time performance. MATLAB simulations are run to evaluate the Bit Error Rate (BER) deterioration of the architecture. The float- and fixed-point simulation results have shown that, The BER deteriorations are less than 0.5 dB and 1 dB, respectively. Further, the implementation of the architecture on a Xilinx XC7VX485T FPGA chip is achieved. A 20 giga bit per second (Gbps) 16 Quadrature Amplitude Modulation (16QAM) real-time system is achieved at the system clock of 159.524 MHz. This work opens a new pathway to improve the transmission capacity in real-time wireless communication systems.

A Novel CDR-Based Low-Cost Time-Interleaved-ADC Timing Calibration

Digital signal processing (DSP)-based system is a common architecture for high-speed communication links. One of the most important components for DSP-based architectures is the analog-to-digital convertor (ADC). Most of the high-speed ADCs are implemented as time interleaved ADC (TI-ADC). One of the major challenges in TI-ADC is the timing mismatch between the parallel sub-ADCs. The calibration of this mismatch increases system cost and complexity. In this article we propose a new background calibration method based on existing clock and data recovery (CDR) circuits. The timing mismatch can be calibrated using a simple and unique CDR per sub-ADC. Using the existing phase error detector and pulse gain estimator of the regular CDR, the calibration circuit becomes very low-cost, requiring only a first order loop, and a slow numerically controlled oscillator (NCO). VCSEL-based lab experiments are performed, which demonstrate the proposed method efficiency, performance and robustness.

A smart DPLL for robust carrier tracking systems using uncertain rule-based IT2 fuzzy controllers

The carrier tracking synchronizes the receiver and transmitter oscillators with each other’s and is adopted as a closed-loop structure known as the phase-locked loop (PLL). Fading, abrupt phase and frequency changes and relative speed between receiver and transmitter (user dynamics resultant from receiver vibrations) are some bottlenecks of robust carrier tracking. In tracking schemes that are used in a noisy environment and high user dynamics, bandwidth considerations are challenging. In this paper, uncertain rule-based interval type-2 (IT2) fuzzy controllers are utilized to handle the existence bandwidth contradiction in carrier tracking schemes in harsh applications. The proposed digital PLL (DPLL) is designed using a modified numerically-controlled oscillator (NCO) for better noise immunity. The designed IT2 fuzzy controllers determine optimal DPLL loop filter coefficients and consequently bandwidth to reject noise, handle user dynamics, and sustain locked. The suggested DPLL is simulated with Xilinx System Generator and indicates effective responses to various test signals such as phase and frequency steps, frequency ramp and added sinusoidal jitter stimuli with fast acquisition and improved pull-in range.

Parallel wideband digital up‐conversion architecture with efficiency

Owing to the limited processing speed of current digital signal processing devices, digital generated signal frequency and bandwidth based on digital up-conversion technique has long been a bottleneck. Interpolation on the baseband signal puts great pressure on the following filtering and mixing operation. In this study, an efficient parallel architecture is presented, which moves the interpolation behind the filtering and mixing, and adopts parallel numerically controlled oscillator (NCO) arrays and poly-phase low-pass filter arrays to achieve the anticipated orthogonal mixing signal and prototype filter. Parallel NCO decomposition principle and mathematical derivation are elaborated, and realisation of the poly-phase filter arrays is also discussed. The proposed post-interpolation architecture can effectively relieve the filtering and mixing pressure including operation rate and computational complexity, which will benefit the hardware implementation. In the end, verification test of signal up-conversion with 400 MHz bandwidth is launched to certify the architecture validity.

Secure Satellite Communication Digital IF CMOS $Q$ -Band Transmitter and $K$ -Band Receiver

This paper reports the first CMOS RF integrated chipset for secure commercial and military satellite communication enabling next-generation low size, weight, and power (SWaP) terminals. This chipset is a significant departure from current terminals relying on individually qualified IC components by taking advantage of advanced CMOS integration. The transmitter and receiver designs are digital IF architectures that rely on the higher sampling rate capability of CMOS, and precise digital filtering, quadrature frequency translation, and frequency hopping/de-hopping. The CMOS transmitter is a fully integrated system-on-chip (SoC) design, while the receiver consists of a co-designed RF and digital IF receiver. The Tx/Rx uses a 200-/300-MHz double data rate (DDR) interface driving/receiving a complex frequency translator with sub-hertz frequency hopping resolution via on-chip numerically controlled oscillators (NCO). The transmitter includes two 12-b return-to-zero (RZ) digital-to-analog converters (DACs) and quadrature modulator to form a single-sideband (SSB) upconverter achieving >30-dB spur rejection. An RF upconverter with an X2 multiplier drives a 24-dBm $Q$ -band CMOS stacked power amplifier (PA). The RF receiver implements a matched inverter amplifier (IA) followed by a complementary active balun that current drives a passive mixer with a trans-impedance active combiner. The digital IF receiver includes a high-linearity variable gain amplifier (VGA) that drives an 8 $\times $ time-interleaved 1.2-GS/s analog-to-digital converter (ADC) with dc offset and gain calibration with an embedded digital receiver. Both the transmitter and receiver use a 1.5-GHz IF signal. The combined CMOS chipset was demonstrated with a current military satcom modulation and protocol and achieves 5 $\times $ lower power consumption and size versus the current configuration.

Carrier phase prediction method for GNSS precise positioning in challenging environment

Since the signals of global navigation satellite system (GNSS) are blocked frequently in challenging environments, the discontinuous carrier phases seriously affect the application of GNSS precise positioning. To improve the carrier phase continuity, this paper proposes a carrier phase prediction method based on carrier open-loop tracking. In the open-loop tracking mode, the carrier numerically controlled oscillator (NCO) is controlled by the predicted Doppler, but not by the loop filter output. To improve the phase prediction effective time, accurate receiver clock drift estimation is studied in the prediction method. The phase prediction performance is tested on GNSS software receiver. In the phase prediction effective time tests, open-loop processes were set for the tested channel. The test results show that, when some satellite signals are blocked in 15 s, the probability of carrier phase error less than quarter cycles is more than 94%. In the real time kinematic (RTK) positioning tests, some satellite signals are blocked in 10–15 s repeatedly. The test results show that, the carrier phase continuity is basically not affected by the signal interruption, and the RTK can almost keep continuous centimeter-level positioning accuracy without re-fixing the integer ambiguity.

GNSS/MEMS IMU ultra‐tightly integrated navigation system based on dual‐loop NCO control method and cascaded channel filters

A coherent scheme of federated architecture for the ultra-tight integration of global navigation satellite system (GNSS) and MEMS (micro-electro-mechanical system) inertial measurement unit (IMU) is presented. Inside the receiver baseband, both the controls for code numerically controlled oscillator (NCO) and carrier NCO are designed. They are each composed of two parts, one part is derived from the navigation solutions of outer loop, and the other part is given on the basis of the channel pre-filter outputs from inner loop. Each tacking channel has two filters of cascaded structure, one is the traditional pre-filter which is used to achieve GNSS signal tracking errors, and the second one is an extractor which is constructed to extract navigation solution derivation errors from the designed NCO controls and the signal tracking errors. For the ultra-tight integration navigation filter, the receiver clock residual error model after compensating the receiver clock drift is derived in detail. Finally, semi-physical simulation environment of the proposed ultra-tight integration scheme is built and closed-loop experiment under high dynamics scenario is put forward. The simulation results show that the proposed integration scheme can stably and robustly track the GNSS signals, and can achieve accurate navigation solutions even in harsh cases.

An All-Programmable 16-nm RFSoC for Digital-RF Communications

The Xilinx RFSoC is the first product to integrate cutting-edge RF data converters with an FPGA SoC. This breakthrough integration delivers a dramatic reduction in system power and footprint, while offering increased flexibility for wide-bandwidth communications applications. The RFSoC monolithically integrates a quad-core 1.5-GHz ARM Cortex-A53 application processor, dual-core Cortex-R5 real-time processing units, 4,000 FPGA DSP resources, and up to 16 digital-RF transmit and receive paths. Each RF transmit path includes a 14-bit, 6.4-GS/s RF-DAC and a flexible digital up conversion (DUC) chain. The RF receive channels contain 12-bit, 4-gigasamples per second (GS/s) RF-ADCs and a flexible digital down conversion (DDC) chain. All RF paths include a programmable complex digital mixer with numerically controlled oscillator (NCO), digital compensation of RF paths, on-chip RF-clock generation, and a flexible wideband interface to the FPGA fabric. The device is housed in a 40x40-mm, 1,517-pin ball grid array (BGA) package and is manufactured in a 16-nm Fin field-effect transistor (FinFET) process.

Decomposing Numerically Controlled Oscillator in Parallel Digital Down Conversion Architecture

The speed of digital signal processing device restricts the performance of the serial digital down conversion (DDC) architecture when the input of the DDC features a high sampling rate. As a result, the polyphase or parallel structure is adopted to relieve the speed pressure. This paper mainly studies the numerically controlled oscillator (NCO) decomposing in the parallel DDC structure, which can decompose the NCO’s output into several branch signals which then can lower the operating speed of the mixer and the low pass filter (LPF) significantly, making it easier to implement DDC with field programmable gate array (FPGA). The mathematical expressions of the branch NCO outputs applied to the parallel DDC are deduced and the selection principles of the correlated parameters are discussed. The simulation and the experimental results of MATLAB show the corrections of the NCO decomposing technique.

Robust Clock Timing Recovery for Performance Improvement in Digital Self-Synchronous OFDM Receivers

Due to constraints of cost and size for mobile devices, a digital self-synchronous OFDM receiver is preferable in mobile applications since it only requires economical crystal oscillators plus free-running analog front-end circuits. However, there are more stringent requirements for clock timing recovery tasks in such a self-synchronous receiver. This paper presents an efficient and robust clock timing recovery scheme for the digital self-synchronous OFDM receiver. It is based on the canonical Gardner structure, but new techniques are devised for performance improvement. A joint iterative estimation algorithm is used for error detection, which can not only improve the detection precision, but also maintain the loop's dynamic performance. A direct control method based on a simple dynamic delay technique instead of the numerical-controlled oscillator mechanism is adopted to smoothly adjust the timing recovery by adaptively performing asynchronous resampling on the discrete sequence of the received signal. Theoretical analysis and numerical simulation results are also presented to verify the effectiveness of the proposed clock timing recovery scheme and conduct performance analysis and evaluation.