Number Of Gate Fingers Research Articles

The impact of induced gate noise when simultaneously power and conjugate noise-matching MOS transistors

A method for simultaneously power matching and conjugate noise matching a MOS transistor for radio frequency applications is presented in this paper. Experimental results from a 0.6 /spl mu/m nMOS transistor show that the magnitude of input reactance equals the optimum noise reactance (i.e., X/sub in/=X/sub opt/). Using this result, the author provides a method that can be used to match the optimum noise resistance to the source resistance. The described method uses the number of gate fingers as a parameter to conjugately match for noise.

Improving threshold-voltage uniformity of0.1 µm InP-based MODFETs with different gate layouts

It is shown that the threshold-voltage uniformity of 0.1 µm InAlAs/InGaAs-based modulation-doped field-effect transistors with different numbers of gate fingers and different gate widths can be improved when a thin cap-layer structure is employed. This improvement is based on the reduction of the recess time. This reduction suppresses the difference in etching that results from the different etching rates caused by the different electrochemical effects that occur because of the varied gate layouts.