Number Of Control Signals Research Articles

Percolation-induced explosive synchronization in pinning control

Percolation and synchronization are two paradigmatic examples of phase transitions that can take place in network dynamical systems. In this paper, we show how percolation can induce an explosive, first-order transition to synchronization in pinning control, a classical feedback strategy that exploits the network topology to drive the network dynamics to a desired synchronous solution. When the number of control signals is limited by physical or economical constraints, only a fraction of the network nodes can be effectively synchronized onto the desired trajectory. Determining the sensitivity of this fraction to the number of pinning control signals is then key to decide if it is worth adding additional control signals. We find that when the network graph percolates, that is, it becomes endowed with a giant strongly connected component (GSCC), an explosive transition to synchronization occurs as we increase the fraction of nodes where we can inject the pinning signals. Motivated by this numerical observation, we exploit the probabilistic conditions that ensure the presence of a GSCC to predict the number of pinning signals such that all of its nodes will converge to the desired synchronous trajectory. We test the validity and robustness of our analytical derivations through numerical simulations on both synthetic and real networks, proving the benefit of such analysis in supporting decision-making for control design.

The walking and running control of a human musculoskeletal model using a low-power consumption hardware central pattern generator model

Applying a control system with low energy consumption and low load of motion control to robots, similar to living organisms, is considered to be one of the most important issues in robot development. We have been studying systems that use pulse-type hardware neural networks to control robotic motion with a small number of control signals, as is the case in living organisms. In particular, it has been mimicking the function of the central pattern generator localized in the spinal cord of living organisms to generate motion patterns. In the present article, a new biomimetic control system using pulse-type hardware neural networks for biped gait control is reported.

No-instruction-set-computer design experience of flexible and efficient architectures for digital communication applications: two case studies on MIMO turbo detection and universal turbo demapping

The emerging flexibility need in designing application-specific processors dedicated for modules of digital receiver imposes a new design metric, which is added to the requirements of efficiency and productivity. In order to cope with the emerging flexibility requirement combined with the best performance efficiency, many application-specific processor design approaches have been proposed and investigated. In general, available design approaches that adopt dynamic scheduling of instructions add an overhead due to the instruction decoding. To minimize this overhead, several approaches have been introduced, which opt static scheduling. In this context, No-Instruction-Set-Computer (NISC) concept has been introduced to design application-specific processors without an instruction set. NISC concept proposes that there is no need to first design and then use an instruction set when the hardware is programmed by its designers rather than its users. NISC designing approach offers a good compromise between flexibility, productivity, and quality for the design of a digital system. In our work, NISC approach is explored through the design of flexible and efficient architectures dedicated for digital communication applications which fulfill the requirements imposed by multiple emergent communication standards. This paper introduces briefly the NISC concept and the corresponding design methodology. Also, it provides an overview of the related design approach. In addition, the relevance of NISC in realizing flexible and efficient implementation in the domain of digital communication is demonstrated through two case studies on MIMO turbo detection and universal turbo demapping. Both designed NISC-based architectures have been compared to state-of-the-art ASIP-based architectures using similar computational resources and supporting same flexibility parameters. The obtained results show that the proposed NISC-based architectures provide a significant improvement in execution performance while having reduced implementation costs. The results also illustrates how the control memory requirements depend on the application and the devised architecture choices. In the detector module, the adopted re-usability of allocated resources imposes separate controlling of each component; hence, additional control signals are implied. Whereas for the demapper module, implemented hardware components are considered to perform specific operations and to deal with the same type of data; hence, the number of control signals can be reduced significantly.

Fractional-order two-component oscillator: stability and network synchronization using a reduced number of control signals

In this paper, a fractional-order version of a chaotic circuit made simply of two non-idealized components operating at high frequency is presented. The fractional-order version of the Hopf bifurcation is found when the bias voltage source and the fractional-order of the system increase. Using Adams–Bashforth–Moulton predictor–corrector scheme, dynamic behaviors are displayed in two complementary types of stability diagrams, namely the two-parameter Lyapunov exponents and the isospike diagrams. The latest being a more fruitful type of stability diagrams based on counting the number of spikes contained in one period of the periodic oscillations. These two complementary types of stability diagrams are reported for the first time in the fractional-order dynamical systems. Furthermore, a new fractional-order adaptive sliding mode controller using a reduced number of control signals was built for the stabilization of a fractional-order complex dynamical network. Two examples are shown on a fractional-order complex dynamical network where the nodes are made of fractional-order two-component circuits. Firstly, we consider an ideal channel, and secondly, a non ideal one. In each case, increasing of the coupling strength leads to the phase transition in the fractional-order complex network.Graphical abstract

Development and computer based simulation of pneumatic conveying control system

The paper presents a review of the core components of the container delivery system in technological products, covering the control signals necessary for the operation of the pneumatic transport system. The functional scheme of the pneumatic container delivery system has been developed, and the number of control signals has been optimized. A schematic diagram of the pneumatic transport control system was developed and a computer based simulation was performed.

Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic

In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm2.

Probabilistic modeling and analysis of molecular memory

This article investigates the aspects of designing a nanocell based molecular memory. An empirical model for molecular device is developed, based on circuit behavior of nitro-substituted Oligo (Phynylene Ethynylene) molecule (OPE). This device model is subsequently used to design nanocell based 1-bit memory and verified using HSPICE. The approach is extended to train the nanocell for multibit storage capability using external voltage signals. It is observed that to successfully train a 2-bit molecular memory, the number of control signals should be approx. one-fourth of total number of nanoparticles. A computational framework is proposed to compute the probability of retrieving the stored data bits correctly, at the output terminal of the nanocell buffer. This nanocell configuration is simulated by systematically varying number of nanoparticles and molecular switches. It is observed that the probability of the existence of at least one path from input to output approaches close to unity with presence of 20 or more nanoparticles in a nanocell. During memory model validation, 1000 samples of 1-bit memory (consisting of 20 nanoparticles) were generated and verified for read and write operations. The model verification results obtained for this memory cell closely match those obtained using analytical solution of probabilistic graph model.

Reversible Architecture of Computer Arithmetic

Reversible logic plays an important role in emerging low power designs and quantum computing. This paper presents an efficient way to realize reversible arithmetic circuits especially targeting toward reversible arithmetic logic unit (RALU). In literature for reversible logic, not a significant advancement is found in integrating both logical and arithmetical functions, commonly known as arithmetic logic unit (ALU), a key feature of any computing system architecture. Here, this work presents a novel reversible arithmetic logic unit (ALU) performing basic functions similar to classical ALU such as addition, subtraction, AND, OR and XOR operations. Additional functions such as, NAND, NOR, XNOR and logical functions with single input inverted, overflow detection and comparison can also be performed with this design. The integration of these operations in single module using less number of control signals is not available in any of existing approaches. The design and analysis based on different parameters of reversible circuits – number of gates, garbage bits and quantum cost as well as simulation results are presented here. The proposed design offers efficient programmability and more flexibility than other methods. General Terms Arithmetic design and logic structures.

Synchronization of Fractional-Order Systems of the Lorenz type: The Non- adaptive Case

This paper presents a synchronization method for fractional order systems of the Lorenz type with known parameters. First we include a study of the isolated behavior of the fractional order Lorenz system (FOLS). Then a master and a slave FOLS are considered and appropriate control signals are designed and applied to the slave system, in order to achieve the synchronization of both systems. These control signals were designed applying the extended Routh-Hurwitz criterion to fractional order systems (FOSs). Simulation results show that synchronization is achieved when all control signals are used, as well as when a reduced number of control signals are employed.

Design of a 12-bit high-speed CMOS D/A converter using a new 3D digital decoder structure useful for wireless transmitter applications

In this paper a 12-bit Nyquist current-steering digital-to-analog converter (DAC) is implemented using TSMC 0.35 μm standard CMOS process technology. The proposed DAC is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for it leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1 GHz sampling frequency. Simulations indicate that the DAC has an accuracy better than 10.7-bit for upcoming higher data rate standards (IEEE 802.16 and 802.11n), and a spurious-free-dynamic-range (SFDR) higher than 64 dB in whole Nyquist frequency band. The post layout four corner Monte-Carlo simulated INL is better than 0.74 LSB while simulated DNL is better than 0.49 LSB. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. Active area of chip is 1.37 mm2.

A 12-Bit 1-Gsample/s Nyquist Current-Steering DAC in 0.35 µm CMOS for Wireless Transmitter

The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 µm CMOS technology. Active area of chip is 1.37 mm2.

A novel continuous genetic algorithm for the solution of optimal control problems

AbstractIn this paper, the Continuous Genetic Algorithm (CGA), previously developed by the principal author, is applied for the solution of optimal control problems. The optimal control problem is formulated as an optimization problem by the direct minimization of the performance index subject to constraints, and is then solved using CGA. In general, CGA uses smooth operators and avoids sharp jumps in the parameter values. This novel approach possesses two main advantages when compared to other existing direct and indirect methods that either suffer from low accuracy or lack of robustness. First, our method can be applied to optimal control problems without any limitation on the nature of the problem, the number of control signals, and the number of mesh points. Second, high accuracy can be achieved where the performance index is globally minimized while satisfying the constraints. The applicability and efficiency of the proposed novel algorithm for the solution of different optimal control problems is investigated. Copyright © 2010 John Wiley & Sons, Ltd.

Very high-speed and high-accuracy current-steering CMOS D/A converter using a novel 3-D decoder

In this paper a 10-bit 1.2-GSample/s Nyquist current-steering CMOS digital-to-analog converter (DAC) is presented. Segmentation (90%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a novel 3-D thermometer decoding method which reduces the area, power consumption, and the number of control signals of the digital section. Simulation results show that the spurious-free-dynamic-range (SFDR) in Nyquist rate is better than 65 dB for sampling frequency up to 1.2-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates at only 2.4 V. Total power consumption in Nyquist rate measurement is 149 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.97 mm2.

Fault diagnosis of alignment networks using Petri nets

Abstract A Petri net model of a multistage cube alignment network is proposed and its use in fault diagnosis is discussed. Existing fault diagnosis methods necessitate the isolation of networks for the performance of tests ; they are also complex and tedious for large network sizes. In comparison, the proposed method envisages on-line testing, requires the setting of a smaller number of control signals, and is easy to implement.

Pulse-echo method of investigating the properties of mechanical resonators

Vibrational sensors can be designed in such a way that the frequency of one of their modes of vibration is a function of temperature, pressure, density, or other parameter, making them the basis of various instrumentation transducers. These can be driven remotely by means of a line carrying bursts of plane waves of stress analogous to sonar or radar. The simple analysis of such a system, where only one mode at a time is considered, is unsatisfactory, and a complete general theory has been developed. This applies to an extended object with an arbitrary pattern of resonant frequencies, internal energy losses, and mechanical couplings to the line. The basic Navier–Stokes equation of motion was solved for this boundary-value problem to give a pole-zero diagram for the system. Computer programs were used to invert the function into the time domain and plot the echo-return traces. The theory has been used to relate experimental observations of the spectra of isotropic disks of a variety of materials to recent theoretical studies. Accurate values of elastic constants and their temperature coefficients have been obtained. The special case of a line resonator, which has a harmonic spectrum, enables the internal friction losses to be evaluated absolutely. To make an automatic system where the drive frequency follows the resonant frequency, a number of control signals are possible. A computer program was prepared to determine the parameters of the various phase control loops available. Subject Classification: 40.24.

Linear control with incomplete state feedback and known initial-state statistics†

A method is proposed for the design of a linear, time-invariant state feedback control for a linear, time-invariant, finite-dimensional system with infinite duration of control (regulator problem), which makes use of only those state variables which are available for measurement, providing that these are sufficient to render the system stable. The expected value vector and the covariance matrix for the initial state are presumed to be known. The cost function is quadratic and is expressed in terms of the initial state statistics and the cost-weighting matrix. The necessary conditions are derived for the minimization of the expected value of the cost. The minimization results in a set of m simultaneous polynomial equations in m unknowns where m is the product of the number of the available state variables and the number of control signals formed out of these. The theory is illustrated by a simple example of a third-order system.