Number Of Coding Bits Research Articles

Design, Implementation and Evaluation of a Low Redundant Error Correction Code

The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common method to tolerate errors in this element is the use of Error Correction Codes (ECC). The addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to allow detecting and/or correcting errors. ECC can be designed with different parameters in mind: low redundancy, low delay, error coverage, etc. The idea of this paper is to study the effects produced when adding an ECC to a microprocessor with respect to overheads. Usually, ECC with different characteristics are continuously proposed. However, a great quantity of these proposals only present the ECC, not showing its behavior when using them in a microprocessor. In this work, we present the design of an ECC whose main characteristic is a low number of code bits (low redundancy). Then, we study the overhead this ECC introduces. Firstly, we show a study of silicon area, delay and power consumption of encoder and decoder circuits, and secondly, how the addition of this ECC affects to a RISC microprocessor.

An Initial Dot Encoding Scheme with Significantly Improved Robustness and Numbers

Coded mark point, as an important part of automatic matching, is widely used in stereo vision and photogrammetry. An encoding scheme named the Initial Dot encoding scheme, has been designed based on the programme of concentric rings, and which is able to solve restrictions on the number of codes and promote the stability of decoding. The designed coding pattern includes three functional points: locating point, start point and coded point. The maximum coding number of the Initial Dot scheme can reach 262,144 when the number of code bits is 18. The recognition experiments show that the Initial Dot encoding scheme can achieve 100% recognition rate at a 75 degree angle, which is very difficult for other coding schemes. By comparing experiments with the Schneider encoding scheme for a large flexible panel, the recognition rate of the proposed scheme is 99%, which is higher than the recognition rate of 90% of the Schneider scheme. The experimental results indicate that the Initial Dot encoding scheme can be successfully applied on flexible solar panels under a 1000 mm × 500 mm field of view.

A High Throughput Implementation of QC-LDPC Codes for 5G NR

Quasi-cyclic low-density parity-check (QC-LDPC) codes are the choice for data channels in the fifth generation (5G) new radio (NR). At the transmitter side, code bits from the QC-LDPC encoder are delivered to the rate matcher. The task of the rate matcher is to select an appropriate number of code bits via puncturing and/or repetition. Code bits that are not selected do not need to be encoded. At the receiver side, the de-rate matcher combines code bits of different transmission attempts and sends them to the QC-LDPC decoder. The output of the QC-LDPC decoder only needs to include necessary systematic bits. Unnecessary systematic bits and parity bits can be completely removed from the decoding process. Taking these considerations into account, a smaller sub-base matrix instead of a full-base matrix can be used in the encoding and decoding process. In this paper, we propose an efficient implementation of QC-LDPC codes for 5G NR. The full-base matrix is pruned before being used. Compared to the traditional schemes, the proposed scheme improves the throughput of QC-LDPC codes in 5G NR.

A Universal Grammar-Based Code for Lossless Compression of Binary Trees

We consider the problem of lossless compression of binary trees, with the aim of reducing the number of code bits needed to store or transmit such trees. A lossless grammar-based code is presented, which encodes each binary tree into a binary codeword in two steps. In the first step, the tree is transformed into a context-free grammar from which the tree can be reconstructed. In the second step, the context-free grammar is encoded into a binary codeword. The decoder of the grammar-based code decodes the original tree from its codeword by reversing the two encoding steps. It is shown that the resulting grammar-based binary tree compression code is a universal code on a family of probabilistic binary tree source models satisfying certain weak restrictions.

Very low bit rate video compression using MPEG‐4 sprite coding

AbstractThe new MPEG‐4 image coding standard that has recently been established offers higher image quality in low‐bit‐rate coding than conventional coding methods such as H.26X, MPEG‐1, and MPEG‐2, as well as coding for each object unit (a new function).This paper proposes an algorithm for the automatic extraction of video objects consisting of a foreground object and a background sprite. It is based on “sprite coding,” which can greatly reduce the number of code bits compared to conventional methods. The foreground and background video objects processed by the proposed method are subjected to MPEG‐4 object coding and sprite coding, respectively, and are compared with MPEG‐4 simple profile (normal) coding. In particular, the influence of the frame rate and the foreground object rate on the number of code bits was investigated. It was found that the proposed method can reproduce images with the same quality while using about one‐fourth to one‐half as many code bits as the normal coding method when the foreground rate is 10 to 15% of the whole image, regardless of the frame rate. In addition, the proposed method can attain more than double the frame rate of the normal coding method at a very low bit rate (e.g., 128 and 64 kbit/s) with a similar SNR. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 86(6): 83–93, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10158

AZTDIS — a two-phase real-time ECG data compressor

An ECG sampled at a rate of 360 samples s −1 or more produces a large amount of redundant data that are difficult to store and transmit; we therefore need a process to represent the signals with clinically acceptable fidelity and with as small a number of code bits as possible. In this paper, a real-time ECG data-compression algorithm, AZTDIS, is presented. AZTDIS is an efficient algorithm which locates significant samples and at the same time encodes linear segments between them by using linear interpolation. The significant samples selected include, but are not limited to, the samples that have significant displacement from the encoded signal such that the allowed maximal error is limited to a constant ϵ, which is specified by the user. The way that AZTDIS computes the displacement of a sample from the encoded signal guarantees that the high activity regions are more accurately coded. The results from AZTDIS are compared with those from the well-known data-compression algorithm, AZTEC, which is also a real-time algorithm. It is found that under the same bit rate, a considerable improvement of root-mean-square error (RMS err) can be achieved by employing the proposed AZTDIS algorithm. An average value of RMS err of 9.715 can be achieved even at an average bit rate of 0.543 bits per sample by employing AZTDIS. By tuning the allowed maximal error of AZTDIS such that it has similar bit rate to AZTEC, the average value of RMS err achieved by AZTDIS is 5.554 while the average value of RMS err achieved by AZTEC under the same bit rate is 19.368.